JAJSGJ3E November 2018 – August 2023 DAC60501 , DAC70501 , DAC80501
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
STATIC PERFORMANCE | ||||||
Resolution | DAC80501 | 16 | Bits | |||
DAC70501 | 14 | |||||
DAC60501 | 12 | |||||
INL | Integral nonlinearity(1) | –1 | 1 | LSB | ||
DNL | Differential nonlinearity(1) | –1 | 1 | LSB | ||
TUE | Total unadjusted error(1) | DAC80501, reference divider disabled (REF-DIV bit = 0) | –0.08 | –0.02 | 0.08 | %FSR |
DAC80501, reference divider enabled (REF-DIV bit = 1) | –0.06 | 0.025 | 0.06 | |||
DAC80501, DGS package reference divider enabled (REF-DIV bit = 1) | –0.07 | 0.025 | 0.07 | |||
DAC70501, DAC60501 | –0.1 | 0.04 | 0.1 | |||
Zero code error(1) | DAC loaded with zero scale code | –1.5 | 0.5 | 1.5 | mV | |
Zero code error temperature coefficient(1) | ±2 | µV/°C | ||||
Offset error(1) | –1.5 | 0.5 | 1.5 | mV | ||
Offset error temperature coefficient (1) | ±2 | µV/°C | ||||
Gain error(1) | DAC80501, reference divider disabled (REF-DIV bit = 0) | –0.08 | –0.02 | 0.08 | %FSR | |
DAC80501, reference divider enabled (REF-DIV bit = 1) | –0.06 | 0.025 | 0.06 | |||
DAC80501, DGS package reference divider enabled (REF-DIV bit = 1) | –0.07 | 0.025 | 0.07 | |||
DAC70501, DAC60501 | –0.1 | 0.04 | 0.1 | |||
Gain error temperature coefficient(1) | ±1 | ppm FSR/°C | ||||
Full-scale error(1) | DAC80501, DAC loaded with full scale, reference divider disabled (REF-DIV bit = 0) | –0.08 | –0.02 | 0.08 | %FSR | |
DAC80501, DAC loaded with full scale, reference divider enabled (REF-DIV bit = 1) | –0.06 | 0.025 | 0.06 | |||
DAC80501, DGS package reference divider enabled (REF-DIV bit = 1) | –0.07 | 0.025 | 0.07 | |||
DAC70501, DAC60501 | –0.1 | 0.04 | 0.1 | |||
Full-scale error temperature coefficient(1) | ±2 | ppm FSR/°C | ||||
OUTPUT CHARACTERISTICS | ||||||
VO | Output voltage | BUFF-GAIN bit set to 1, REF-DIV bit set to 0 | 0 | 2 × VREFIO | V | |
BUFF-GAIN bit set to 1, REF-DIV bit set to 1 | 0 | VREFIO | ||||
BUFF-GAIN bit set to 0, REF-DIV bit set to 1 | 0 | 0.5 × VREFIO | ||||
RLOAD | Resistive load(2) | VDD = 2.7 V | 0.25 | kΩ | ||
VDD = 5.5 V | 0.5 | |||||
CLOAD | Capacitive load(2) | RLOAD = infinite | 2 | nF | ||
RLOAD = 2 kΩ | 10 | |||||
Load regulation | DAC at midscale, –10 mA ≤ IOUT ≤ 10 mA | 80 | µV/mA | |||
Short circuit current | Full scale output shorted to AGND | 30 | mA | |||
Zero output shorted to VDD | 30 | |||||
Output voltage headroom | to VDD, DAC at full code, IOUT = 10 mA (sourcing) | 0.3 | 0.1 | V | ||
Output voltage footroom | to AGND, DAC at zero code, IOUT = 10 mA (sinking) | 0.3 | V | |||
ZO | DC small signal output impedance | DAC at midscale | 0.1 | Ω | ||
DAC at code 256 | 10 | |||||
DAC at code 65279 | 10 | |||||
Power supply rejection ratio (DC) | DAC at midscale; VDD = 5 V ± 10% | 0.15 | mV/V | |||
Output voltage drift vs time | TA = 35°C, VOUT = midscale, 1900 hr | 20 | ppm of FSR | |||
VOLTAGE REFERENCE INPUT | ||||||
ZVREFIO | Reference input impedance (VREFIO) | 100 | kΩ | |||
CVREFIO | Reference input capacitance (VREFIO) | 5 | pF | |||
VOLTAGE REFERENCE OUTPUT | ||||||
Output (initial accuracy)(3) | TA = 25°C | 2.4975 | 2.5025 | V | ||
Output drift(3) | DAC80501 | 5 | ppm/℃ | |||
DAC70501, DAC60501 | 10 | |||||
Output impedance(3) | 0.1 | Ω | ||||
Output noise(3) | 0.1 Hz to 10 Hz | 14 | µVPP | |||
Output noise density(3) | Measured at 10 kHz, reference load = 10 nF | 140 | nV/√ Hz | |||
Load current(3) | –0.5 mV < ΔVref < 0.5 mV | ±5 | mA | |||
Load regulation(3) | Sourcing and sinking | 90 | µV/mA | |||
Line regulation(3) | 20 | µV/V | ||||
Output voltage drift vs time(3) | TA = 25°C, 1600 hr | 50 | ppm of FSR | |||
Thermal hysteresis(3) | 1st cycle | 500 | µV | |||
Additional cycle | 25 | µV | ||||
DYNAMIC PERFORMANCE | ||||||
ts | Output voltage settling time(4) | ¼ to ¾ scale and ¾ to ¼ scale settling to ±2 LSB, VDD = 5.5 V, VREFIO = 2.5 V | 5 | µs | ||
10-mV settling to ±2 LSB, VDD = 5.5 V, VREFIO = 2.5 V | 3 | |||||
Slew rate(4) | VDD = 5.5 V, VREFIO = 2.5 V | 2 | V/µs | |||
Power on glitch magnitude | CLOAD = 50 pF | 200 | mV | |||
Vn | Output noise(4) | 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V, external VREFIO = 2.5 V | 14 | µVPP | ||
100-kHz Bandwidth, DAC at midscale, VDD = 5.5 V, external VREFIO = 2.5 V | 23 | µVrms | ||||
Vn | Output noise density | Measured at 1 kHz, DAC at
midscale, VDD = 5.5 V, external VREFIO = 2.5 V, gain = 2 × (BUFF-GAIN bit = 1) | 78 | nV/√ Hz | ||
Measured at 10 kHz, DAC at
midscale, VDD = 5.5 V, external VREFIO = 2.5 V, gain = 2 × (BUFF-GAIN bit = 1) | 74 | |||||
Measured at 1 kHz, DAC at full
scale, VDD = 2.7 V, external VREFIO = 2.5 V, gain = 1 × (BUFF-GAIN bit = 0) | 55 | |||||
Measured at 10 kHz, DAC at
full scale, VDD = 2.7 V, external VREFIO = 2.5 V, gain = 1 × (BUFF-GAIN bit = 0) | 50 | |||||
SFDR | Spurious free dynamic range | 1-kHz sinusoid at DAC output, DAC updated at 500 kHz, include up to 7th harmonics, no filter on DAC output | 70 | dB | ||
THD | Total harmonic distortion | 1-kHz sinusoid at DAC output, DAC updated at 500 kHz, include up to 7th harmonics, no filter on DAC output | 70 | dB | ||
Power supply rejection ratio (ac) | 200-mV 50-Hz to 60-Hz sine wave superimposed on power supply voltage, DAC at midscale. (ac analysis) | 85 | dB | |||
Code change glitch impulse | Midcode ±1 LSB (including feedthrough) | 4 | nV-s | |||
Code change glitch magnitude | Midcode ±1 LSB (including
feedthrough) gain = 1 × (BUFF-GAIN bit = 0) | 7.5 | mV | |||
Digital feedthrough | At SCLK = 1 MHz, DAC output at midscale | 4 | nV-s | |||
DIGITAL INPUTS | ||||||
Hysteresis voltage | 0.4 | V | ||||
Input current | –5 | 5 | µA | |||
Pin capacitance | Per pin | 10 | pF | |||
POWER REQUIREMENTS | ||||||
IVDD | Current flowing into VDD | Normal mode, internal reference enabled, DAC at full scale, SPI static | 1.5 | 2.0 | mA | |
Normal mode, external reference = 2.5 V, DAC at full scale, SPI static | 1 | 1.4 | ||||
DAC and Internal reference power-down | 15 | µA | ||||
IVREFIO | Current flowing into VREFIO | 0-V to 5-V range, midscale code | 25 | µA |