JAJSSA9 November 2023 DAC61401 , DAC81401
PRODUCTION DATA
Table 7-2 lists the memory-mapped registers for the device. All register offset addresses not listed in Table 7-2 are reserved locations. Do not modify the register contents.
Offset | Acronym | Register Name | Section |
---|---|---|---|
00h | NOP | NOP Register | Go |
01h | DEVICEID | DEVICE ID Register | Go |
02h | STATUS | STATUS Register | Go |
03h | SPICONFIG | SPI CONFIG Register | Go |
04h | GENCONFIG | GENERAL CONFIG Register | Go |
09h | DACPWDWN | DAC POWER DOWN Register | Go |
0Ah | DACRANGE | DAC RANGE Register | Go |
0Eh | TRIGGER | TRIGGER Register | Go |
10h | DAC | DAC DATA Register | Go |
NOP is shown in Figure 7-1 and described in Table 7-3.
Return to Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NOP[15:0] | |||||||||||||||
W-0000h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | NOP | W | 0000h |
No operation. Write 0000h for proper no-operation command |
The device ID is shown in Figure 7-2 and described in Table 7-4.
Return to Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DEVICEID[13:6] | |||||||
R | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DEVICEID[5:0] | VERSIONID[1:0] | ||||||
R-00h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:2 | DEVICEID | R | 029Ch or 024Ch |
Device ID |
1:0 | VERSIONID | R | 0h |
Version ID. Subject to change |
The status register is shown in Figure 7-3 and described in Table 7-5.
Return to Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-00h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRC-ALM | DAC-BUSY | TEMP-ALM | ||||
R-00h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:3 | RESERVED | N/A | 0h |
Reserved |
2 | CRC-ALM | R | 0h |
CRC Alarm 0: no error in CRC 1: CRC error indicated |
1 | DAC-BUSY | R | 0h |
DAC Busy 0: DAC is ready for update 1: DAC is not ready for update |
0 | TEMP-ALM | R | 0h |
Temperature Alarm 0: No thermal alarm 1: Die temperature is over +140°C. A thermal alarm event forces the DAC output to go into power-down mode |
The SPI configuration register is shown in Figure 7-4 and described in Table 7-6.
Return to Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TEMPALM-EN | DACBUSY-EN | CRCALM-EN | RESERVED | |||
R-0h | R/W-1h | R/W-0h | R/W-1h | R-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DEV-PWDWN | CRC-EN | RESERVED | SDO-EN | FSDO | RESERVED | |
R-1h | R-0h | R/W-1h | R/W-0h | R-0h | R/W-1h | R/W-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R | 0h | Reserved |
11 | TEMPALM-EN | R/W | 1h |
Temperature alarm enable 0: Thermal alarm does not trigger the FAULT pin 1: Thermal alarm triggers the FAULT pin |
10 | DACBUSY-EN | R/W | 0h |
DAC busy indicator enable 0: No DAC busy indicator 1: The FAULT pin is set between DAC output updates. This alarm resets automatically |
9 | CRCALM-EN | R/W | 1h |
CRC alarm enable 0: No CRC alarm indicator 1: A CRC error triggers the FAULT pin |
8:6 | RESERVED | R | 2h | Reserved |
5 | DEV-PWDWN | R/W | 1h |
Device power-down enable 0: The device is in active mode 1: The device is in power-down mode |
4 | CRC-EN | R/W | 0h |
CRC enable 0: No CRC 1: frame error checking is enabled |
3 | RESERVED | R | 0h | Reserved |
2 | SDO-EN | R/W | 1h |
SDO pin enable 0: The SDO pin is not operational 1: The SDO pin is operational |
1 | FSDO | R/W | 0h |
Fast SDO bit enable 0: SDO updates on SCLK rising edges 1: SDO updates on SCLK falling edges |
0 | RESERVED | R | 0h | Reserved |
The general configuration register is shown in Figure 7-5 and described in Table 7-7.
Return to Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | REF-PWDWN | RESERVED | |||||
R-0h | R/W-1h | R-00h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-00h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 0h | Reserved |
14 | REF-PWDWN | R/W | 1h |
Reference power down 0: Internal reference enabled 1: Internal reference disabled |
13:0 | RESERVED | R | 0000h | Reserved |
The DAC power-down register is shown in Figure 7-6 and described in Table 7-8.
Return to Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-FFh | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DAC-PWDWN | ||||||
R-FFh | R/W-1h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:1 | RESERVED | N/A | FFFFh |
Reserved |
0 | PDN | R/W | 0h |
DAC power down bit 0: DAC is enabled 1: DAC is powered down and the output is connected to ground through a 10-kΩ internal resistor |
The DAC range register is shown in Figure 7-7 and described in Table 7-9.
Return to Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
N/A-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DAC-RANGE3:0 | ||||||
N/A-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:4 | RESERVED | N/A | 000h |
Reserved |
3:0 | DAC-RANGE | R/W | 0h |
Sets the output
range for the corresponding DAC. |
The trigger register is shown in Figure 7-8 and described in Table 7-10.
Return to Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SOFT-CLR | ALM-RESET | |||||
W-00h | W-0h | W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SOFT-RESET[3:0] | ||||||
W-0h | W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:10 | RESERVED | W | 00h | Reserved |
9 | SOFT-CLR | W | 0h |
Software clear of the DAC output 0: DAC output remains unchanged 1: DAC output is cleared |
8 | ALM-RESET | W | 0h | Set this bit to 1 to clear an alarm event. Not applicable for a DAC-BUSY alarm event |
7-4 | RESERVED | W | 0h | Reserved |
3:0 | SOFT_RESET | W | 0h | Set these bits to reserved code 0b1010 to reset the device to the default state |
The DAC data register is shown in Figure 7-9 and described in Table 7-11.
Return to Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DAC-DATA[15:0] | |||||||||||||||
W-0000h |
Bit | Field | Type | Reset | Desc |
---|---|---|---|---|
DAC-DATA | W | 0h |
Stores the 16-bit
or 12-bit data to be loaded to DAC in MSB-aligned
straight-binary format. |