JAJSE84D June   2017  – August 2018 DAC60508 , DAC70508 , DAC80508

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 9.3.1.1 DAC Transfer Function
        2. 9.3.1.2 Output Amplifiers
        3. 9.3.1.3 DAC Register Structure
          1. 9.3.1.3.1 DAC Register Synchronous and Asynchronous Updates
          2. 9.3.1.3.2 Broadcast DAC Register
          3. 9.3.1.3.3 CLEAR Operation (DACx0508C only)
      2. 9.3.2 Internal Reference
        1. 9.3.2.1 Reference Divider
        2. 9.3.2.2 Solder Heat Reflow
      3. 9.3.3 Device Reset Options
        1. 9.3.3.1 Power-on-Reset (POR)
        2. 9.3.3.2 Software Reset
    4. 9.4 Device Functional Modes
      1. 9.4.1 Stand-Alone Operation
      2. 9.4.2 Daisy-Chain Operation
      3. 9.4.3 Frame Error Checking
      4. 9.4.4 Power-Down Mode
    5. 9.5 Programming
    6. 9.6 Register Map
      1. 9.6.1 NOP Register (address = 0x00) [reset = 0x0000]
        1. Table 9. NOP Register Field Descriptions
      2. 9.6.2 DEVICE ID Register (address = 0x01) [reset = 0x---]
        1. Table 10. DEVICE ID Field Descriptions
      3. 9.6.3 SYNC Register (address = 0x2) [reset = 0xFF00]
        1. Table 11. SYNC Register Field Descriptions
      4. 9.6.4 CONFIG Register (address = 0x3) [reset = 0x0000]
        1. Table 12. CONFIG Register Field Descriptions
      5. 9.6.5 GAIN Register (address = 0x04) [reset = 0x---]
        1. Table 13. GAIN Register Field Descriptions
      6. 9.6.6 TRIGGER Register (address = 0x05) [reset = 0x0000]
        1. Table 14. TRIGGER Register Field Descriptions
      7. 9.6.7 BRDCAST Register (address = 0x6) [reset = 0x0000]
        1. Table 15. BRDCAST Register Field Descriptions
      8. 9.6.8 STATUS Register (address = 0x7) [reset = 0x0000]
        1. Table 16. STATUS Register Field Descriptions
      9. 9.6.9 DACx Register (address = 0x8 to 0xF) [reset = 0x0000 or 0x8000]
        1. Table 17. DACx Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Interfacing to Microcontroller
      2. 10.1.2 Programmable Current Source Circuit
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 関連リンク
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.5 Programming

The DACx0508 is controlled through a flexible serial interface that is compatible with SPI type interfaces used on many microcontrollers and DSP controllers. Table 7 shows the SPI timing requirements. Figure 65 and Figure 66 show the SPI write and read timing diagrams, respectively.

Table 7. Programming Timing Requirements(1)

VIO = 1.7 V to 2.7 V VIO = 2.7 V to 5.5 V UNIT
MIN NOM MAX MIN NOM MAX
SERIAL INTERFACE – WRITE OPERATION
fSCLK SCLK frequency 50 50 MHz
tSCLKHIGH SCLK high time 9 9 ns
tSCLKLOW SCLK low time 9 9 ns
tSDIS SDI setup 5 5 ns
tSDIH SDI hold 10 10 ns
tCSS CS to SCLK falling edge setup 13 13 ns
tCSH SCLK falling edge to CS rising edge 10 10 ns
tCSHIGH CS high time 15 15 ns
tCSIGNORE SCLK falling edge to CS ignore 7 7 ns
SERIAL INTERFACE – READ AND DAISY CHAIN OPERATION, FSDO = 0
fSCLK SCLK frequency 12 18 MHz
tSCLKHIGH SCLK high time 35 25 ns
tSCLKLOW SCLK low time 35 25 ns
tSDIS SDI setup 5 5 ns
tSDIH SDI hold 10 10 ns
tCSS CS to SCLK falling edge setup 32 20 ns
tCSH SCLK falling edge to CS rising edge 10 10 ns
tCSHIGH CS high time 15 15 ns
tSDODLY SDO output delay from SCLK rising edge 3.5 33.5 3.5 23 ns
tSDODZ SDO driven to tri-state 0 30 0 25 ns
tCSIGNORE SCLK falling edge to CS ignore 7 7 ns
SERIAL INTERFACE – READ AND DAISY CHAIN OPERATION, FSDO = 1
fSCLK SCLK frequency 20 25 MHz
tSCLKHIGH SCLK high time 22 18 ns
tSCLKLOW SCLK low time 22 18 ns
tSDIS SDI setup 5 5 ns
tSDIH SDI hold 10 10 ns
tCSS CS to SCLK falling edge setup 32 20 ns
tCSH SCLK falling edge to CS rising edge 10 10 ns
tCSHIGH CS high time 15 15 ns
tSDODLY SDO output delay from SCLK falling edge 3.5 45 3.5 32 ns
tSDODZ SDO driven to tri-state 0 30 0 25 ns
tCSIGNORE SCLK falling edge to CS ignore 7 7 ns
DIGITAL LOGIC
tRSTDLYPOR POR reset delay 170 250 170 250 µs
tDACWAIT Sequential DAC output updates 1 1 µs
tCLR CLR pulse 20 20 ns
tCLRD CLR delay(2) 100 100 ns
(1) All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VIO), timed from a voltage level of (VIL + VIH)/2, VDD = 2.7 V to 5.5 V, VIO = 1.7 V to 5.5 V, VREFIN = 1.25 V to 5.5 V, SDO loaded with 20 pF, TA = -40°C to +125°C
(2) Specified from a logic-low on CLR pin to when the DAC output starts to change. In the special case when the DAC output is at GND or VDD, the CLR delay may be as long as 1 µs
DAC80508 DAC70508 DAC60508 timing1_slase73.gifFigure 65. Serial Interface Write Timing Diagram
DAC80508 DAC70508 DAC60508 timing2_slase73.gifFigure 66. Serial Interface Read Timing Diagram