JAJS498D August   2008  – August 2023 DAC5311 , DAC6311 , DAC7311

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Device Comparison
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements
    7. 7.7  Timing Diagrams
    8. 7.8  Typical Characteristics: AVDD = 5 V
    9. 7.9  Typical Characteristics: AVDD = 3.6 V
    10. 7.10 Typical Characteristics: AVDD = 2.7 V
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Section
      2. 8.3.2 Resistor String
      3. 8.3.3 Output Amplifier
      4. 8.3.4 Power-On Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Input Shift Register
        2. 8.5.1.2 SYNC Interrupt
  10. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Microprocessor Interfacing
        1. 9.1.1.1 DACx311 to 8051 Interface
        2. 9.1.1.2 DACx311 to Microwire Interface
        3. 9.1.1.3 DACx311 to 68HC11 Interface
    2. 9.2 Typical Applications
      1. 9.2.1 Loop Powered Transmitter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Using the REF5050 as a Power Supply for the DACx311
      3. 9.2.3 Bipolar Operation Using the DACx311
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Typical Characteristics: AVDD = 5 V

at TA = 25°C, AVDD = 5 V, and DAC loaded with midscale code (unless otherwise noted)

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Figure 7-2 DAC7311 12-Bit Linearity Error and Differential Linearity Error vs Code (–40°C)
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Figure 7-4 DAC7311 12-Bit Linearity Error and Differential Linearity Error vs Code (25°C)
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Figure 7-6 DAC7311 12-Bit Linearity Error and Differential Linearity Error vs Code (125°C)
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Figure 7-8 DAC5311 8-Bit Linearity Error and Differential Linearity Error vs Code (–40°C)
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Figure 7-10 DAC5311 8-Bit Linearity Error and Differential Linearity Error vs Code (25°C)
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Figure 7-12 DAC5311 8-Bit Linearity Error and Differential Linearity Error vs Code (125°C)
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Figure 7-14 Source Current at Positive Rail
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Figure 7-16 Power-Supply Current vs Digital Input Code
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Figure 7-18 Power-Supply Current vs Temperature
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Figure 7-20 Total Harmonic Distortion vs Output Frequency
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Figure 7-22 Power Spectral Density
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Figure 7-24 DAC Output Noise, 0.1-Hz to 10-Hz Bandwidth
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Figure 7-26 Glitch Energy, 5-V, 12-Bit, 1-LSB Step, Rising Edge
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Figure 7-28 Glitch Energy, 5-V, 8-Bit, 1-LSB Step, Rising Edge
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Figure 7-30 Full-Scale Settling Time, 5-V Rising Edge
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Figure 7-32 Half-Scale Settling Time, 5-V Rising Edge
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Figure 7-34 Power-On Reset to 0-V Power-On Glitch
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Figure 7-36 Power-Supply Current vs Power-Supply Voltage
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Figure 7-38 Power-Supply Current Histogram
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Figure 7-3 DAC6311 10-Bit Linearity Error and Differential Linearity Error vs Code (–40°C)
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Figure 7-5 DAC6311 10-Bit Linearity Error and Differential Linearity Error vs Code (25°C)
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Figure 7-7 DAC6311 10-Bit Linearity Error and Differential Linearity Error vs Code (125°C)
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Figure 7-9 Zero-Code Error vs Temperature
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Figure 7-11 Offset Error vs Temperature
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Figure 7-13 Full-Scale Error vs Temperature
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Figure 7-15 Sink Current at Negative Rail
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Figure 7-17 Power-Supply Current vs Logic Input Voltage
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Figure 7-19 Power-Down Current vs Temperature
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Figure 7-21 Signal-to-Noise Ratio vs Output Frequency
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Figure 7-23 DAC Output Noise Density vs Frequency
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Figure 7-25 Clock Feedthrough, 5-V, 2-MHz, Midscale
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Figure 7-27 Glitch Energy, 5-V, 12-Bit, 1-LSB Step, Falling Edge
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Figure 7-29 Glitch Energy, 5-V, 8-Bit, 1-LSB Step, Falling Edge
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Figure 7-31 Full-Scale Settling Time, 5-V Falling Edge
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Figure 7-33 Half-Scale Settling Time 5-V Falling Edge
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Figure 7-35 Power-Off Glitch
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Figure 7-37 Power-Down Current vs Power-Supply Voltage