JAJSSA9A November   2023  – December 2024 DAC61401 , DAC81401

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements - Write, IOVDD = 1.7V to 2.7V
    7. 5.7  Timing Requirements - Write, IOVDD = 2.7V to 5.5V
    8. 5.8  Timing Requirements - Read and Daisy Chain, FSDO = 0, IOVDD = 1.7V to 2.7V
    9. 5.9  Timing Requirements - Read and Daisy Chain, FSDO = 1, IOVDD = 1.7V to 2.7V
    10. 5.10 Timing Requirements - Read and Daisy Chain, FSDO = 0, IOVDD = 2.7V to 5.5V
    11. 5.11 Timing Requirements - Read and Daisy Chain, FSDO = 1, IOVDD = 2.7V to 5.5V
    12. 5.12 Timing Diagrams
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converter (DAC) Architecture
      2. 6.3.2 R-2R Ladder DAC
      3. 6.3.3 Programmable Gain Output Buffer
      4. 6.3.4 Sense Pins
      5. 6.3.5 DAC Register Structure
        1. 6.3.5.1 Output Update
        2. 6.3.5.2 Software Clear
          1. 6.3.5.2.1 Software Reset Mode
      6. 6.3.6 Internal Reference
      7. 6.3.7 Power-Supply Sequence
        1. 6.3.7.1 Power-On Reset (POR)
      8. 6.3.8 Thermal Alarm
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power Down Mode
    5. 6.5 Programming
      1. 6.5.1 Stand-Alone Operation
      2. 6.5.2 Daisy-Chain Operation
      3. 6.5.3 Frame Error Checking
  8. 7 Register Map
    1. 7.1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Key Components
        2. 8.2.2.2 Compensation Capacitor
        3. 8.2.2.3 Gain Stage
        4. 8.2.2.4 Attenuation and Buffer Stage
        5. 8.2.2.5 External Power Supply
        6. 8.2.2.6 Protection Design
        7. 8.2.2.7 Design Accuracy
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RTE|16
  • PW|20
サーマルパッド・メカニカル・データ
発注情報

7.1 Registers

Table 7-2 lists the memory-mapped registers for the device. All register offset addresses not listed in Table 7-2 are reserved locations. Do not modify the register contents.

Table 7-2 Registers
Offset Acronym Register Name Section
00h NOP NOP Register Go
01h DEVICEID DEVICE ID Register Go
02h STATUS STATUS Register Go
03h SPICONFIG SPI CONFIG Register Go
04h GENCONFIG GENERAL CONFIG Register Go
09h DACPWDWN DAC POWER DOWN Register Go
0Ah DACRANGE DAC RANGE Register Go
0Eh TRIGGER TRIGGER Register Go
10h DAC DAC DATA Register Go

7.1.1 NOP Register (Offset = 00h) [reset = 0000h]

NOP is shown in Figure 7-1 and described in Table 7-3.

Return to Summary Table.

Figure 7-1 NOP Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NOP[15:0]
W-0000h
Table 7-3 NOP Register Field Descriptions
Bit Field Type Reset Description
15:0 NOP W 0000h

No operation. Write 0000h for proper no-operation command

7.1.2 DEVICEID Register (Offset = 01h) [reset = 0A70h or 0930h]

The device ID is shown in Figure 7-2 and described in Table 7-4.

Return to Summary Table.

Figure 7-2 DEVICEID Register
15 14 13 12 11 10 9 8
DEVICEID[13:6]
R
7 6 5 4 3 2 1 0
DEVICEID[5:0] VERSIONID[1:0]
R-00h R-0h
Table 7-4 DEVICEID Register Field Descriptions
Bit Field Type Reset Description
15:2 DEVICEID R 029Ch or 024Ch

Device ID
029C: DAC81401 (16 Bits)
024C: DAC61401 (12 Bits)
1:0 VERSIONID R 0h

Version ID. Subject to change

7.1.3 STATUS Register (Offset = 02h) [reset = 0000h]

The status register is shown in Figure 7-3 and described in Table 7-5.

Return to Summary Table.

Figure 7-3 STATUS Register
15 14 13 12 11 10 9 8
RESERVED
R-00h
7 6 5 4 3 2 1 0
RESERVED CRC-ALM DAC-BUSY TEMP-ALM
R-00h R-0h R-0h R-0h
Table 7-5 STATUS Register Field Descriptions
Bit Field Type Reset Description
15:3 RESERVED N/A 0h

Reserved
2 CRC-ALM R 0h

CRC Alarm

0: no error in CRC

1: CRC error indicated
1 DAC-BUSY R 0h

DAC Busy

0: DAC is ready for update

1: DAC is not ready for update
0 TEMP-ALM R 0h

Temperature Alarm

0: No thermal alarm

1: Die temperature is over +140°C. A thermal alarm event forces the DAC output to go into power-down mode

7.1.4 SPICONFIG Register (Offset = 03h) [reset = 0AA4h]

The SPI configuration register is shown in Figure 7-4 and described in Table 7-6.

Return to Summary Table.

Figure 7-4 SPICONFIG Register
15 14 13 12 11 10 9 8
RESERVED TEMPALM-EN DACBUSY-EN CRCALM-EN RESERVED
R-0h R/W-1h R/W-0h R/W-1h R-0h
7 6 5 4 3 2 1 0
RESERVED DEV-PWDWN CRC-EN RESERVED SDO-EN FSDO RESERVED
R-1h R-0h R/W-1h R/W-0h R-0h R/W-1h R/W-0h R-0h
Table 7-6 SPICONFIG Register Field Descriptions
Bit Field Type Reset Description
15:12 RESERVED R 0h Reserved
11 TEMPALM-EN R/W 1h

Temperature alarm enable

0: Thermal alarm does not trigger the FAULT pin

1: Thermal alarm triggers the FAULT pin
10 DACBUSY-EN R/W 0h

DAC busy indicator enable

0: No DAC busy indicator

1: The FAULT pin is set between DAC output updates. This alarm resets automatically
9 CRCALM-EN R/W 1h

CRC alarm enable

0: No CRC alarm indicator

1: A CRC error triggers the FAULT pin
8:6 RESERVED R 2h Reserved
5 DEV-PWDWN R/W 1h

Device power-down enable

0: The device is in active mode

1: The device is in power-down mode
4 CRC-EN R/W 0h

CRC enable

0: No CRC

1: frame error checking is enabled
3 RESERVED R 0h Reserved
2 SDO-EN R/W 1h

SDO pin enable

0: The SDO pin is not operational

1: The SDO pin is operational

1 FSDO R/W 0h

Fast SDO bit enable

0: SDO updates on SCLK rising edges

1: SDO updates on SCLK falling edges
0 RESERVED R 0h Reserved

7.1.5 GENCONFIG Register (Offset = 04h) [reset = 0000h]

The general configuration register is shown in Figure 7-5 and described in Table 7-7.

Return to Summary Table.

Figure 7-5 GENCONFIG Register
15 14 13 12 11 10 9 8
RESERVED REF-PWDWN RESERVED
R-0h R/W-1h R-00h
7 6 5 4 3 2 1 0
RESERVED
R-00h
Table 7-7 GENCONFIG Register Field Descriptions
Bit Field Type Reset Description
15 RESERVED R 0h Reserved
14 REF-PWDWN R/W 1h

Reference power down

0: Internal reference enabled

1: Internal reference disabled
13:0 RESERVED R 0000h Reserved

7.1.6 DACPWDWN Register (Offset = 09h) [reset = FFFFh]

The DAC power-down register is shown in Figure 7-6 and described in Table 7-8.

Return to Summary Table.

Figure 7-6 DACPWDWN Register
15 14 13 12 11 10 9 8
RESERVED
R-FFh
7 6 5 4 3 2 1 0
RESERVED DAC-PWDWN
R-FFh R/W-1h
Table 7-8 DACPWDWN Register Field Descriptions
Bit Field Type Reset Description
15:1 RESERVED N/A FFFFh

Reserved
0 PDN R/W 0h

DAC power down bit

0: DAC is enabled

1: DAC is powered down and the output is connected to ground through a 10kΩ internal resistor

7.1.7 DACRANGE Register (Offset = 0Ah) [reset = 0000h]

The DAC range register is shown in Figure 7-7 and described in Table 7-9.

Return to Summary Table.

Figure 7-7 DACRANGE Register
15 14 13 12 11 10 9 8
RESERVED
N/A-0h
7 6 5 4 3 2 1 0
RESERVED DAC-RANGE3:0
N/A-0h R/W-0h
Table 7-9 DACRANGE Register Field Descriptions
Bit Field Type Reset Description
15:4 RESERVED N/A 000h

Reserved
3:0 DAC-RANGE R/W 0h

Sets the output range for the corresponding DAC.
0000: 0V to 5V
1000: 0V to 6V
0001: 0V to 10V
1001: 0V to 12V
0010: 0V to 20V
1010: 0V to 24V
0011: 0V to 40V
0101: –5.0V to +5.0V
1101: –6.0V to +6.0V
0110: –10.0V to +10.0V
1110: –12.0V to +12.0V
0111: –20.0V to +20.0V
All other combinations invalid

7.1.8 TRIGGER Register (Offset = 0Eh) [reset = 0000h]

The trigger register is shown in Figure 7-8 and described in Table 7-10.

Return to Summary Table.

Figure 7-8 TRIGGER Register
15 14 13 12 11 10 9 8
RESERVED SOFT-CLR ALM-RESET
W-00h W-0h W-0h
7 6 5 4 3 2 1 0
RESERVED SOFT-RESET[3:0]
W-0h W-0h
Table 7-10 TRIGGER Register Field Descriptions
Bit Field Type Reset Description
15:10 RESERVED W 00h Reserved
9 SOFT-CLR W 0h

Software clear of the DAC output

0: DAC output remains unchanged

1: DAC output is cleared
8 ALM-RESET W 0h Set this bit to 1 to clear an alarm event. Not applicable for a DAC-BUSY alarm event
7-4 RESERVED W 0h Reserved
3:0 SOFT_RESET W 0h Set these bits to reserved code 0b1010 to reset the device to the default state

7.1.9 DAC Register (Offset = 10h) [reset = 0000h]

The DAC data register is shown in Figure 7-9 and described in Table 7-11.

Return to Summary Table.

Figure 7-9 DAC Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC-DATA[15:0]
W-0000h
Table 7-11 DAC Register Field Descriptions
Bit Field Type Reset Description
DAC-DATA W 0h

Stores the 16-bit data to be loaded to DAC in MSB-aligned straight-binary format.
Data use the following format:
DAC81401: {DATA[15:0]}
DAC61401: {DATA[11:0], x, x, x, x}
x – Don't care bits