JAJSMH1B July   2021  – May 2022 DLP300S

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
    14. 6.14 Software Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Low-Speed Interface
      3. 7.3.3 High-Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Optical Interface and System Image Quality
        1. 7.5.1.1 Numerical Aperture and Stray Light Control
        2. 7.5.1.2 Pupil Match
        3. 7.5.1.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On and Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Device Markings
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Related Links
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-F481B835-6AA6-4A2C-A0C1-70CF2417D98D-low.gifFigure 5-1 FQK Package57-Pin LGA(Bottom View)
Table 5-1 Pin Functions – Connector Pins(1)
PINTYPESIGNALDATA RATEDESCRIPTIONPACKAGE NET LENGTH(2) (mm)
NAMENO.
DATA INPUTS
D_N(0)C9ISubLVDSDoubleData, Negative10.54
D_P(0)B9ISubLVDSDoubleData, Positive10.54
D_N(1)D10ISubLVDSDoubleData, Negative13.14
D_P(1)D11ISubLVDSDoubleData, Positive13.14
D_N(2)C11ISubLVDSDoubleData, Negative14.24
D_P(2)B11ISubLVDSDoubleData, Positive14.24
D_N(3)D12ISubLVDSDoubleData, Negative14.35
D_P(3)D13ISubLVDSDoubleData, Positive14.35
D_N(4)D4ISubLVDSDoubleData, Negative5.89
D_P(4)D5ISubLVDSDoubleData, Positive5.89
D_N(5)C5ISubLVDSDoubleData, Negative5.45
D_P(5)B5ISubLVDSDoubleData, Positive5.45
D_N(6)D6ISubLVDSDoubleData, Negative8.59
D_P(6)D7ISubLVDSDoubleData, Positive8.59
D_N(7)C7ISubLVDSDoubleData, Negative7.69
D_P(7)B7ISubLVDSDoubleData, Positive7.69
DCLK_ND8ISubLVDSDoubleClock, Negative8.10
DCLK_PD9ISubLVDSDoubleClock, Positive8.10
CONTROL INPUTS
LS_WDATAC12ILPSDR(1)SingleWrite data for low speed interface.7.16
LS_CLKC13ILPSDRSingleClock for low-speed interface7.89
DMD_DEN_ARSTZC14ILPSDRAsynchronous reset DMD signal. A low signal places the DMD in reset. A high signal releases the DMD from reset and places it in active mode.
LS_RDATAC15OLPSDRSingleRead data for low-speed interface
POWER(3)
VBIASC1PowerSupply voltage for positive bias level at micromirrors
VBIASC18Power
VOFFSETD1PowerSupply voltage for HVCMOS core logic. Supply voltage for stepped high level at micromirror address electrodes.
Supply voltage for offset level at micromirrors.
VOFFSETD17Power
VRESETB1PowerSupply voltage for negative reset level at micromirrors.
VRESETB18Power
VDDB6Power
VDDB10Power
VDDB19Power
VDDC6PowerSupply voltage for LVCMOS core logic. Supply voltage for LPSDR inputs.
Supply voltage for normal high level at micromirror address electrodes.
VDDC10Power
VDDC19Power
VDDD2Power
VDDD18Power
VDDD19Power
VDDIB2PowerSupply voltage for SubLVDS receivers.
VDDIC2Power
VDDIC3Power
VDDID3Power
VSSB3GroundCommon return.
Ground for all power.
VSSB4Ground
VSSB8Ground
VSSB12Ground
VSSB13Ground
VSSB14Ground
VSSB15Ground
VSSB16Ground
VSSB17Ground
VSSC4Ground
VSSC8Ground
VSSC16Ground
VSSC17Ground
VSSD14Ground
VSSD15Ground
VSSD16Ground
(1) Low speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR)JESD209B.
(2) Net trace lengths inside the package:
Relative dielectric constant for the FQK ceramic package is 9.8.
Propagation speed = 11.8 / sqrt (9.8) = 3.769 inches/ns.
Propagation delay = 0.265 ns/inch = 265 ps/inch = 10.43 ps/mm.
(3) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.
Table 5-2 Pin Functions – Test Pads
NUMBERSYSTEM BOARD
A13Do not connect
A14Do not connect
A15Do not connect
A16Do not connect
A17Do not connect
A18Do not connect
E13Do not connect
E14Do not connect
E15Do not connect
E16Do not connect
E17Do not connect
E18Do not connect