JAJSLD4B august   2020  – july 2023 DLP471TP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Power Density Calculation
    8. 7.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Temperature Sensor Diode
  10. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Impedance Requirements
    3. 10.3 Layers
    4. 10.4 Trace Width, Spacing
    5. 10.5 Power
    6. 10.6 Trace Length Matching Recommendations
  12. 11Device and Documentation Support
    1. 11.1 サード・パーティ製品に関する免責事項
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
      2. 11.2.2 Device Markings
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.6 Trace Length Matching Recommendations

Recommended signal trace length matching requirements can be found in Table 10-4 and Table 10-5. When length matching traces, the longer signals should be routed in a serpentine fashion, keeping the number of turns to a minimum and the turn angles no sharper than 45 degrees as opposed to running long traces over large areas of the PCB.

Signals in Table 10-4 should be routed for data rate operation at up to 3.2 Gbps. Layer changes for these signals should be minimized, the number of vias should be minimized. Avoid sharp turns and layer switching while keeping lengths to a minimum. When layer changes are necessary, GND vias should be placed around the signal vias to provide a signal return path. The distance from one pair of differential signals to another shall be at least 2 times the distance within the pair.

Table 10-4 HSSI High Speed DMD Data Signals
SIGNAL NAMEREFERENCE SIGNALRouting SpecUnit
DMD_HSSI0_N(0...7),
DMD_HSSI0_P(0...7)		DMD_HSSI0_CLK_N,
DMD_HSSI_CLK_P		+/- 0.25inch
DMD_HSSI1_N(0...7),
DMD_HSSI1_P(0...7)		DMD_HSSI0_CLK_N,
DMD_HSSI_CLK_P		+/- 0.25inch
DMD_HSSI0_CLK_PDMD_HSSI1_CLK_P+/- 0.05inch
Intra-pair PIntra-pair N+/- 0.01inch
Table 10-5 Other Timing Critical Signals
SIGNAL NAMEConstraintsRouting Layers
LS_CLK_P, LS_CLK_N
LS_WDATA_P, LS_WDATA_N
LS_RDATA_A		Intra-pair (P to N)
Matched to 0.01 inches
Signal-to-signal
Matched to +/- 0.25 inches		Layers 3, 8