over operating free-air temperature range (unless otherwise noted)PARAMETER(1)(2)(3) | TEST CONDITIONS | MIN | TYP(4) | MAX(5) | UNIT |
---|
I(VDD) + I(VDD_PLLM)
+ I(VDD_PLLD) | 1.1-V rails | Frame rate = 60 Hz | | 69 | 75 | mA |
I(VDD_PLLM) | MCG PLL 1.1-V current6 | Frame rate = 60 Hz | | 6 | | mA |
I(VDD_PLLD) | DCG PLL 1.1-V current6 | Frame rate = 60 Hz | | 6 | | mA |
I(VCC18) | All 1.8-V I/O current: (1.8-V power supply for all I/O other than the
host or parallel interface and the SPI flash interface) | Frame rate = 60 Hz | | 21 | 23 | mA |
I(VCC_INTF) | Host or parallel interface I/O current: 1.8 to 3.3 V (includes IIC0,
PDATA, video syncs, and HOST_IRQ pins)6 | Frame rate = 60 Hz | | 2 | | mA |
I(VCC_FLSH) | Flash interface I/O current: 1.8 to 3.3 V6 | Frame rate = 60 Hz | | 1 | | mA |
(1) Values assume all pins using 1.1 V are tied together (including VDDLP12), and programmable host and flash I/O are at the minimum nominal voltage (that is 1.8 V).
(2) Input image is 640 × 360 (nHD) 24 bits using VESA
reduced blanking v2 timings on the parallel interface at the frame rate shown with the 0.16-in nHD (DLP160CP) DMD. The
controller has the CAIC and LABB algorithms turned off.
(3) The values do not take into account software updates or customer changes that may affect power performance.
(4) Assumes nominal process, voltage, and temperature (25°C nominal ambient) with nominal input images.
(5) Assumes worst case process, maximum voltage, and high nominal ambient temperature of 65°C with worst case input image.
(6) This rail was not measured due to board limitations. Simulation values are used instead. Simulations assume 12.5% activity factor, 30% clock gating on appropriate domains, and mixed SVT (standard threshold voltage) or HVT (high threshold voltage) cells