JAJSLD1C May   2021  – November 2022 DLPC6540

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  DMD HSSI Electrical Characteristics
    8. 6.8  DMD Low-Speed LVDS Electrical Characteristics
    9. 6.9  V-by-One Interface Electrical Characteristics
    10. 6.10 USB Electrical Characteristics
    11. 6.11 System Oscillator Timing Requirements
    12. 6.12 Power Supply and Reset Timing Requirements
    13. 6.13 DMD HSSI Timing Requirements
    14. 6.14 DMD Low-Speed LVDS Timing Requirements
    15. 6.15 V-by-One Interface General Timing Requirements
    16. 6.16 Source Frame Timing Requirements
    17. 6.17 Synchronous Serial Port Interface Timing Requirements
    18. 6.18 Master and Slave I2C Interface Timing Requirements
    19. 6.19 Programmable Output Clock Timing Requirements
    20. 6.20 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    21. 6.21 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
    22. 6.22 Multi-Trace ETM Interface Timing Requirements
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Sources
      2. 7.3.2 Processing Delays
      3. 7.3.3 V-by-One Interface
      4. 7.3.4 DMD (HSSI) Interface
      5. 7.3.5 Program Memory Flash Interface
      6. 7.3.6 GPIO Supported Functionality
      7. 7.3.7 Debug Support
    4. 7.4 Device Operational Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Normal Configuration
  8. Power Supply Recommendations
    1. 8.1 Power Supply Management
    2. 8.2 Hot Plug Usage
    3. 8.3 Power Supplies for Unused Input Source Interfaces
    4. 8.4 Power Supplies
      1. 8.4.1 1.15-V Power Supplies
      2. 8.4.2 1.21V Power Supply
      3. 8.4.3 1.8-V Power Supplies
      4. 8.4.4 3.3-V Power Supplies
  9. Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 General Layout Guidelines
      2. 9.1.2 Power Supply Layout Guidelines
      3. 9.1.3 Layout Guidelines for Internal Controller PLL Power
      4. 9.1.4 Layout Guideline for DLPC6540 Reference Clock
        1. 9.1.4.1 Recommended Crystal Oscillator Configuration
      5. 9.1.5 V-by-One Interface Layout Considerations
      6. 9.1.6 USB Interface Layout Considerations
      7. 9.1.7 DMD Interface Layout Considerations
      8. 9.1.8 General Handling Guidelines for Unused CMOS-Type Pins
      9. 9.1.9 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
    2. 9.2 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Device Nomenclature
        1. 10.1.2.1 Device Markings
        2. 10.1.2.2 Package Data
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
      1. 10.6.1 Video Timing Parameter Definitions
  11. 11Mechanical, Packaging, and Orderable Information
    1.     79

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Pin Configuration and Functions

GUID-5F25FFD2-A8FA-4D0A-8418-3DE75C541FBB-low.gif Figure 5-1 ZDC Package676-Pin PBGATop View
Table 5-1 Initialization, Board Level Test, and Debug
PIN TYPE(1) DESCRIPTION
NAME NO.
POSENSE AE27 I8 Power-On Sense: Signal provided from external voltage monitoring circuit
('0' = All controller supply voltages not at valid level, '1' = All controller supply voltages have reached 90% specified minimum voltage)
Drive this signal to inactive (low) after the falling edge of PWRGOOD as specified. See Section 6.12 for specific timing requirements as well as the required power up and power down sequence.
This pin includes hysteresis.
PWRGOOD AG30 I8 Power Good: Signal provided from external power supply of voltage monitor
A high value indicates all power is within operating voltage specifications and the system is safe to exit its reset state. A transition from high to low indicates that the controller or DMD supply voltage drops below its rated minimum level. This transition must occur prior to the supply voltage dropping per the timing specified, as this is an early warning of an imminent power loss condition.
This warning is required to enhance long term DMD reliability. When PWRGOOD goes low for the specified minimum time, a DMD park and full Controller reset are performed, protecting the DMD. Note that both controller and DMD supply voltages must be within operating voltage levels to successfully execute the DMD park. The minimum PWRGOOD deassertion time is used to protect the system input from glitches. When PWRGOOD is low, the Controller is held in its reset state.
See Section 6.12 for specific timing requirements as well as the required power up and power down sequence.
This pin includes hysteresis.
EXT_ARSTZ AF29 O8 External Reset: General purpose reset output
('0' = Reset, '1' = Normal Operation)
This output is asserted low immediately upon POSENSE being asserted low, and remains low while POSENSE remains low. This signal remains low after POSENSE is set high, until released by software. This signal is also asserted low approximately 5 µs after the detection of PWRGOOD going low, or any internally generated reset. In all cases, this signal remains active low for a minimum of 2 ms.
Note: This signal can also be independently driven through the software register.
MTR_ARSTZ AF27 O8 Color Wheel Motor Controller Reset: Color wheel motor controller reset output
('0' = Reset, '1' = Normal Operation)
This output is asserted low immediately upon POSENSE being asserted low, and remains low while POSENSE remains low. This signal remains low after POSENSE is set high, until released by software. This signal is also asserted low approximately 5 µs after the detection of PWRGOOD going low, or any internally generated reset. In all cases, this signal remains active low for a minimum of 2 ms.
Note: This signal can also be independently driven through the software register.

TCK AK19 I8 JTAG, ARM-ICE, and CPU MBIST Serial Data Clock.
This signal is shared between JTAG, ARM-ICE (TI test only), and CPU MBIST (Manufacturing test only) operation
Includes a weak internal pulldown
TMS1 AH20 I8 JTAG Test Mode Select
Includes a weak internal pullup
TMS2 AJ20 I8 ARM-ICE Test Mode Select
For normal operation, this pin must be left open or unconnected. Includes a weak internal pullup
TMS3 AK20 I8 CPU MBIST Test Mode Select
For normal operation this pin must be left open or unconnected. Includes a weak internal pullup
TRSTZ AG21 I8 JTAG, ARM-ICE, and CPU MBIST Reset.
This signal is shared between JTAG, ARM-ICE (TI test only), and CPU MBIST (Manufacturing test only) operation.
For normal operation, this pin must be pulled to ground through an external resistor with value 8 kΩ or less. Failure to pull this pin low during normal operation causes start-up and initialization problems.
For JTAG Boundary Scan, ARM-ICE Debug operation, or CPU MBIST, this pin must be pulled-up or left disconnected. Includes a weak internal pullup and hysteresis
TDI AG20 I8 JTAG, ARM-ICE, and CPU MBIST: Serial Data In
Includes a weak internal pullup
TDO1 AG19 O8 JTAG Serial Data Out
TDO2 AH19 O8 ARM-ICE Serial Data Out
For normal operation, this pin must be left open or unconnected.
TDO3 AJ19 O8 CPU MBIST Serial Data Out
For normal operation, this pin must be left open or unconnected.
ETM_TRACECLK C30 O8 TI internal use. Must be left unconnected (clock for trace debug)
ETM_TRACECTL D30 O8 TI internal use. Must be left unconnected (control for trace debug)
ICTSEN K26 I8 IC Tristate Enable (Active high)
Asserting this signal transitions all outputs into tristate (except for the JTAG interface).
Includes a weak internal pulldown, however, an external pulldown is recommended for added protection. Also includes hysteresis
ICTSE M26 I8 TI internal use. Includes a weak internal pulldown, however, an external pulldown is recommended for added protection. Also includes hysteresis
TSTPT_0 E29 B8 Test pin 0
This pin requires an external pulldown or pullup resistor (depending on the desired debug output as noted below) with a value of ≤ 10 kΩ.
Tristated while PWRGOOD is asserted low. It may be driven as an output for debug use as described in Section 7.3.7.
TSTPT_1 E30 B8 Test pin 1
This pin requires an external pulldown or pullup resistor (depending on the desired debug output as noted below) with a value of ≤ 10 kΩ.
Tristated while PWRGOOD is asserted low. It may be driven as an output for debug use as described in Section 7.3.7.
TSTPT_2 F26 B8 Test pin 2
This pin requires an external pulldown or pullup resistor (depending on the desired debug output as noted below) with a value of ≤ 10 kΩ.
Tristated while PWRGOOD is asserted low. It can be driven as an output for debug use as described in Section 7.3.7.
TSTPT_3 F27 B8 Test pin 3
This pin requires an external pulldown or pullup resistor (depending on the desired debug output as noted below) with a value of ≤ 10 kΩ.
Tristated while PWRGOOD is asserted low. It may be driven as an output for debug use as described in Section 7.3.7.
TSTPT_4 F28 B8 Test pin 4
This pin requires an external pulldown resistor (≤ 10 kΩ).
Tri-stated while PWRGOOD is asserted low. It can be driven as an output for debug use as described in Section 7.3.7.
TSTPT_5 F29 B8 Test pin 5
This pin requires an external pulldown resistor (≤ 10 kΩ).
Tristated while PWRGOOD is asserted low. It can be driven as an output for debug use as described in Section 7.3.7.
TSTPT_6 G26 B8 Test pin 6
This pin requires an external pulldown resistor (≤ 10 kΩ).
Tristated while PWRGOOD is asserted low. It can be driven as an output for debug use as described in Section 7.3.7.
TSTPT_7 G28 B8 Test pin 7
This pin requires an external pulldown resistor (≤ 10 kΩ).
Tristated while PWRGOOD is asserted low. It can be driven as an output for debug use as described in Section 7.3.7.
HWTEST_EN L26 I8 Manufacturing test enable signal.
This signal must be connected directly to ground on the PCB for normal operation.
Includes a weak internal pulldown and hysteresis
See Table 5-13 for more information on I/O definitions.
Table 5-2 Analog Front End (Not Supported in DLPC6540)
PIN TYPE(1) DESCRIPTION
NAME NO.
AFE_ARSTZ K2 O8 Reserved
AFE_CLK K3 O8 Reserved
AFE_IRQ K4 I8 Reserved
ALF_VSYNC K5 I8 Reserved
ALF_HSYNC J1 I8 Reserved
ALF_CSYNC J2 I8 Reserved
See Table 5-13 for more information on I/O definitions.
Table 5-3 V-by-One Interface Input Data and Control
PIN TYPE(1) DESCRIPTION(2)(3)
NAME NO.
VX1_DATA0_P
VX1_DATA0_N
VX1_DATA1_P
VX1_DATA1_N
VX1_DATA2_P
VX1_DATA2_N
VX1_DATA3_P
VX1_DATA3_N
VX1_DATA4_P
VX1_DATA4_N
VX1_DATA5_P
VX1_DATA5_N
VX1_DATA6_P
VX1_DATA6_N
VX1_DATA7_P
VX1_DATA7_N
C18
D18
A19
B19
C20
D20
A21
B21
C22
D22
A23
B23
C24
D24
A25
B25
I1 V-by-One interface data lanes
VX1_HTPDN E17 O4 V-by-One interface hot plug detect (controller receiver pulls this signal low to indicate its presence to the transmitter)
This signal is open drain at the controller output. A pullup resistor is required at the transmitter.
VX1_LOCKN E19 O4 V-by-One interface clock detect lock (controller receiver pulls this signal low to indicate clock extraction lock to the transmitter)
This signal is open drain at the controller output. A pullup resistor is required at the transmitter.
VX1_CM_CKREF0
VX1_CM_CKREF1
VX1_CM_CKREF2
VX1_CM_CKREF3
E20
E21
E23
E24
I1 V-by-One reserved: Tie these reserved pins to ground.
VX1_CM_AMOUT0
VX1_CM_AMOUT1
VX1_CM_AMOUT2
VX1_CM_AMOUT3
F19
F21
F22
F23
O1 V-by-One reserved: These pins are reserved and must remain unconnected.
See Table 5-13 for more information on I/O definitions.
The system supports 1-lane, 2-lane, 4-lane, or 8-lane operation, based on the bandwidth requirement of the input source. The inputs for any unused data lanes must be left open.
The V-by-One port supports limited lane remapping to help optimize board layout. The details are described in Section 7.3.3.
Table 5-4 OpenLDI (FPD-Link I) (Not Supported in DLPC6540) Ports Input Data and Control
PIN TYPE(1) DESCRIPTION(2)(3)
NAME NO.
FPDA_CLK_P
FPDA_CLK_N
H3
H4
I5 Reserved
FPDA_DATAA_P
FPDA_DATAA_N
FPDA_DATAB_P
FPDA_DATAB_N
FPDA_DATAC_P
FPDA_DATAC_N
FPDA_DATAD_P
FPDA_DATAD_N
FPDA_DATAE_P
FPDA_DATAE_N
G1
G2
F3
F4
E1
E2
D3
D4
C1
C2
I5 Reserved
FPDB_CLK_P
FPDB_CLK_N
A4
B4
I5 Reserved
FPDB_DATAA_P
FPDB_DATAA_N
FPDB_DATAB_P
FPDB_DATAB_N
FPDB_DATAC_P
FPDB_DATAC_N
FPDB_DATAD_P
FPDB_DATAD_N
FPDB_DATAE_P
FPDB_DATAE_N
C5
D5
A6
B6
C7
D7
A8
B8
C9
D9
I5 Reserved
FPDC_CLK_P
FPDC_CLK_N
A10
B10
I5 Reserved
FPDC_DATAA_P
FPDC_DATAA_N
FPDC_DATAB_P
FPDC_DATAB_N
FPDC_DATAC_P
FPDC_DATAC_N
FPDC_DATAD_P
FPDC_DATAD_N
FPDC_DATAE_P
FPDC_DATAE_N
C11
D11
A12
B12
C13
D13
A14
B14
C15
D15
I5 Reserved.
See Table 5-13 for more information on I/O definitions.
Throughout this document the terms FPD and FPD-Link refer to OpenLDI (FPD-Link I).
Tie the inputs for any unused port(s) to ground, or pull to ground through an external resistor.
Table 5-5 Parallel Port Input Data and Control (Not Supported in DLPC6540)
PIN TYPE(1) DESCRIPTION
PARALLEL RGB MODE
NAME NO.
PCLK (FPDB_DATAB_N) B6 I6 Reserved
VSYNC (FPDA_DATAE_P) C1 I6 Reserved
HSYNC (FPDA_DATAE_N) C2 I6 Reserved
DATEN (FPDB_DATAE_N) D9 I6 Reserved(2)
FIELD (FPDC_DATAE_P) C15 I6 Reserved
3D_REF (FPDC_DATAE_N) D15 I6 Reserved
PDATA_A0 (FPDA_CLK_P)
PDATA_A1 (FPDA_CLK_N)
PDATA_A2 (FPDA_DATAA_P)
PDATA_A3 (FPDA_DATAA_N)
PDATA_A4 (FPDA_DATAB_P)
PDATA_A5 (FPDA_DATAB_N)
PDATA_A6 (FPDA_DATAC_P)
PDATA_A7 (FPDA_DATAC_N)
PDATA_A8 (FPDA_DATAD_P)
PDATA_A9 (FPDA_DATAD_N)
H3
H4
G1
G2
F3
F4
E1
E2
D3
D4
I6 Reserved
PDATA_B0 (FPDB_CLK_P)
PDATA_B1 (FPDB_CLK_N)
PDATA_B2 (FPDB_DATAA_P)
PDATA_B3 (FPDB_DATAA_N)
PDATA_B4 (FPDB_DATAB_P)
PDATA_B5 (FPDB_DATAC_P)
PDATA_B6 (FPDB_DATAC_N)
PDATA_B7 (FPDB_DATAD_P)
PDATA_B8 (FPDB_DATAD_N)
PDATA_B9 (FPDB_DATAE_P)
A4
B4
C5
D5
A6
C7
D7
A8
B8
C9
I6 Reserved
PDATA_C0 (FPDC_CLK_P)
PDATA_C1 (FPDC_CLK_N)
PDATA_C2 (FPDC_DATAA_P)
PDATA_C3 (FPDC_DATAA_N)
PDATA_C4 (FPDC_DATAB_P)
PDATA_C5 (FPDC_DATAB_N)
PDATA_C6 (FPDC_DATAC_P)
PDATA_C7 (FPDC_DATAC_N)
PDATA_C8 (FPDC_DATAD_P)
PDATA_C9 (FPDC_DATAD_N)
A10
B10
C11
D11
A12
B12
C13
D13
A14
B14
I6 Reserved
See Table 5-13 for more information on I/O definitions.
If the DATEN is not actively driven, then it must be pulled up to 3.3 V with a weak pullup resistor (50-kΩ max).
Table 5-6 DMD Reset and Low Speed Interfaces
PIN TYPE(1) DESCRIPTION
NAME NO.
DMD_LS0_CLK_P
DMD_LS0_CLK_N
AH17
AG17
O2 DMD low speed differential interface, Port 0 Clock
DMD_LS0_WDATA_P
DMD_LS0_WDATA_N
AK16
AJ16
O2 DMD low speed differential interface, Port 0 Write Data
DMD_LS1_CLK_P
DMD_LS1_CLK_N
AH15
AG15
O2 DMD low speed differential interface, Port 1 Clock (2)
DMD_LS1_WDATA_P
DMD_LS1_WDATA_N
AK14
AJ14
O2 DMD low speed differential interface, Port 1Write Data (2)
DMD_LS0_RDATA AH13 I3 DMD, low speed single ended serial interface, Port 0 Read Data (3)
DMD_LS1_RDATA AG13 I3 DMD, low speed single ended serial interface, Port 1 Read Data (2)(3). If this port is not used, this signal requires an external pullup or pulldown to keep this input from floating.
DMD_DEN_ARSTZ AK12 O3 DMD driver enable signal / Active Low Asynchronous Reset
('1' = Enabled, '0' = Reset)
This signal is driven low after the DMD is parked and before power is removed from the DMD.
If the 1.8-V power to the DLPC6540 is independent of the 1.8-V power to the DMD, then an external pulldown resistor must be used to hold the signal low in the event the DLPC6540 power is inactive while DMD power is applied.
See Table 5-13 for more information on I/O definitions.
DMD LS1 port is reserved for single controller, two DMD applications.
All control interface reads make use of the single ended low speed signals. The read data is clocked by the low speed differential write clock.
Table 5-7 DMD HSSI (High Speed Serial Interface)
PIN (1) TYPE(2) DESCRIPTION
NAME NO.
DMD_HSSI0_CLK_P
DMD_HSSI0_CLK_N
AK25
AJ25
O7 DMD high speed serial interface, Port 0 Clock Lane
DMD_HSSI0_D0_P
DMD_HSSI0_D0_N
DMD_HSSI0_D1_P
DMD_HSSI0_D1_N
DMD_HSSI0_D2_P
DMD_HSSI0_D2_N
DMD_HSSI0_D3_P
DMD_HSSI0_D3_N
DMD_HSSI0_D4_P
DMD_HSSI0_D4_N
DMD_HSSI0_D5_P
DMD_HSSI0_D5_N
DMD_HSSI0_D6_P
DMD_HSSI0_D6_N
DMD_HSSI0_D7_P
DMD_HSSI0_D7_N
AK29
AJ29
AH28
AG28
AK27
AJ27
AH26
AG26
AH24
AG24
AK23
AJ23
AH22
AG22
AK21
AJ21
O7 DMD high speed serial interface, Port 0 Data Lanes
DMD_HSSI1_CLK_P
DMD_HSSI1_CLK_N
AH7
AG7
O7 DMD high speed serial interface, Port 1 Clock Lane
DMD_HSSI1_D0_P
DMD_HSSI1_D0_N
DMD_HSSI1_D1_P
DMD_HSSI1_D1_N
DMD_HSSI1_D2_P
DMD_HSSI1_D2_N
DMD_HSSI1_D3_P
DMD_HSSI1_D3_N
DMD_HSSI1_D4_P
DMD_HSSI1_D4_N
DMD_HSSI1_D5_P
DMD_HSSI1_D5_N
DMD_HSSI1_D6_P
DMD_HSSI1_D6_N
DMD_HSSI1_D7_P
DMD_HSSI1_D7_N
AH11
AG11
AK10
AJ10
AH9
AG9
AK8
AJ8
AK6
AJ6
AH5
AG5
AK4
AJ4
AK2
AJ2
O7 DMD high speed serial interface, Port 1 Data Lanes
HSSI_ATETEST AJ12 O7 Manufacturing Test use only—Must be left open (that is, unconnected)
A number of pin remapping options are available for the HSSI high speed channels to aid with optimizing board signal routing. See Section 7.3.4 for information on these pin remapping options.
See Table 5-13 for more information on I/O definitions.
Table 5-8 Program Memory (FLASH) Interface
PIN TYPE(1) DESCRIPTION
NAME NO.
PM_CSZ_0 T27 O8 Chip select: boot FLASH only (Boot FLASH must use this chip select.)
PM_CSZ_1 T28 O8 Chip select: additional peripheral device
PM_CSZ_2 T29 O8 Chip select: additional peripheral device
PM_ADDR_0 T30 O8 Address bit (LSB)
PM_ADDR_1 U26 O8 Address bit
PM_ADDR_2 U27 O8 Address bit
PM_ADDR_3 U29 O8 Address bit
PM_ADDR_4 U30 O8 Address bit
PM_ADDR_5 V29 O8 Address bit
PM_ADDR_6 V28 O8 Address bit
PM_ADDR_7 V27 O8 Address bit
PM_ADDR_8 V26 O8 Address bit
PM_ADDR_9 W30 O8 Address bit
PM_ADDR_10 W29 O8 Address bit
PM_ADDR_11 W28 O8 Address bit
PM_ADDR_12 W26 O8 Address bit
PM_ADDR_13 Y30 O8 Address bit
PM_ADDR_14 Y29 O8 Address bit
PM_ADDR_15 Y28 O8 Address bit
PM_ADDR_16 Y27 O8 Address bit
PM_ADDR_17 Y26 O8 Address bit
PM_ADDR_18 AA30 O8 Address bit
PM_ADDR_19 AA29 O8 Address bit
PM_ADDR_20 AA27 O8 Address bit
PM_ADDR_21 AA26 O8 Address bit
PM_ADDR_22 AB29 O8 Address bit
PM_ADDR_23 (GPIO_47) AB28 B8 Address bit (MSB)(2)
PM_WEZ R28 O8 Write enable (active low)
PM_OEZ R29 O8 Output enable (active low)
PM_BLSZ_0 R30 O8 Lower Byte (7:0) Enable (active low)—only applicable to devices using PM_CSZ_1 or PM_CSZ_2
PM_BLSZ_1 T26 O8 Upper Byte (15:8) Enable (active low)—only applicable to devices using PM_CSZ_1 or PM_CSZ_2
PM_Data_0 L29 B8 Data bit
PM_Data_1 L30 B8 Data bit
PM_Data_2 L28 B8 Data bit
PM_Data_3 M27 B8 Data bit
PM_Data_4 M28 B8 Data bit
PM_Data_5 M29 B8 Data bit
PM_Data_6 M30 B8 Data bit
PM_Data_7 N26 B8 Data bit
PM_Data_8 N27 B8 Data bit
PM_Data_9 N29 B8 Data bit
PM_Data_10 N30 B8 Data bit
PM_Data_11 P26 B8 Data bit
PM_Data_12 P27 B8 Data bit
PM_Data_13 P28 B8 Data bit
PM_Data_14 P29 B8 Data bit
PM_Data_15 R26 B8 Data bit
See Table 5-13 for more information on I/O definitions.
The Program Memory address bus can be extended by one bit to 24 bits by making use of GPIO_47. Add an external pulldown resistor when this GPIO is configured for this purpose.
Table 5-9 Peripheral Interfaces
PIN TYPE(1) DESCRIPTION
NAME NO.
IIC0_SCL E27 B13 I2C Port 0 (master-slave), Typically slave for Host Command and Control to Controller, SCL (bidirectional, open-drain): An external pullup is required. The minimum acceptable value for this pullup is 1 KΩ.
IIC0_SDA D29 B13 I2C Port 0 (master-slave), Typically slave for Host Command and Control to Controller, SDA. (bidirectional, open-drain): An external pullup is required. The minimum acceptable value for this pullup is 1 KΩ.
SSP0_TXD AD27 O8 SSP/SPI Port 0 Data Out (master): transmit data pin
SSP0_RXD AD29 I8 SSP/SPI Port 0 Data In (master): Receive data pin
SSP0_CLK AD28 O8 SSP/SPI Port 0 clock (master): clock pin
SSP0_CSZ_2 AC28 O8 SPI Port 0 chip select 2 (master): chip select (active low)
An external pullup resistor (≤ 100 kΩ) is suggested to avoid a floating chip select input to the external device.
SSP0_CSZ_1 AC26 O8 SPI Port 0 chip select 1 (master): chip select (active low)
An external pullup resistor (≤ 100 kΩ) is suggested to avoid a floating chip select input to the external device.
SSP0_CSZ_0 AB27 O8 SPI Port 0 chip select 0 (master): chip select (active low)
An external pullup resistor (≤ 100 kΩ) is suggested to avoid a floating chip select input to the external device.
UART0_TXD P4 O8 UART Port 0 (slave): serial data transmit
This UART port is reserved for TI debug. An external pullup resistor (≤ 10 kΩ) is required.
UART0_RXD P5 I8 UART Port 0 (slave): serial data receive
This UART port is reserved for TI debug. An external pullup resistor (≤ 10 kΩ) is required.
UART0_RTSZ N2 O8 UART Port 0 (slave): ready to send (hardware flow control signal [active low])
This UART port is reserved for TI debug. An external pullup resistor (≤ 10 kΩ) is required.
UART0_CTSZ N3 I8 UART Port 0 (slave): clear to send (hardware flow control signal [active low])
This UART port is reserved for TI debug. An external pullup resistor (≤ 10 kΩ) is required.
USB_DAT_P
USB_DAT_N
B27
A27
B11 USB OTG Data Lane (master-slave)
USB_VBUS D26 B11 USB OTG 5V Power Supply Detection (master-slave)
USB_ID C27 IOther USB OTG Mini Receptacle Identification (master-slave)
USB_TXRTUNE C26 BGND USB OTG Reference Resistor
An external reference resistor must be connected as shown in Section 9.1.6.
USB_XI A29 IGND USB OTG External Oscillator XI—Not used (clock provided internally)
For normal operation this pin must be connected to GND.
USB_XO B29 BGND USB OTG External Oscillator XO—Not used (clock provided internally)
For normal operation this pin must be left open (unconnected).
USB_ANALOGTEST C28 BOther USB OTG Manufacturing Test
This pin must be left open (unconnected).
PMD_INTZ AD26 I8 Reserved function. This signal requires an external pullup.
CW_PWM AE30 O8 Reserved function
CW_INDEX AE29 I8 Reserved function
See Table 5-13 for more information on I/O definitions.
Table 5-10 GPIO Peripheral Interface
PIN TYPE(1) DESCRIPTION(2)(3)(4)
NAME NO.
GPIO_87 K1 B8 General purpose I/O 87: Options:
  1. Alt 0: Reserved
  2. Alt 1: DAO_CLKIN (I)
  3. Optional GPIO
GPIO_86 L5 B8 General purpose I/O 86: Options:
  1. Alt 0: Reserved
  2. Alt 1: DAO_DI_1 (I)
  3. Optional GPIO
GPIO_85 L4 B8 General purpose I/O 85: Options:
  1. Alt 0: Reserved
  2. Alt 1: DAO_DI_0 (I)
  3. Optional GPIO
GPIO_84 L3 B8 General purpose I/O 84: Options:
  1. Alt 0: Reserved
  2. Alt 1: HBT_CLKIN_2 (I)
  3. Optional GPIO
GPIO_83 L2 B8 General purpose I/O 83: Options:
  1. Alt 0: Reserved
  2. Alt 1: HBT_DI_2 (I)
  3. Optional GPIO
GPIO_82 M5 B8 General purpose I/O 82: Options:
  1. Alt 0: Reserved
  2. Alt 1: HBT_CLKIN_1 (I)
  3. Optional GPIO
GPIO_81 M4 B8 General purpose I/O 81: Options:
  1. Alt 0: Reserved
  2. Alt 1: HBT_DI_1 (I)
  3. Optional GPIO
GPIO_80 M2 B8 General purpose I/O 80: Options:
  1. Alt 0: Reserved
  2. Alt 1: HBT_CLKIN_0 (I)
  3. Optional GPIO
GPIO_79 M1 B8 General purpose I/O 79: Options:
  1. Alt 0: Reserved
  2. Alt 1: HBT_DI_0 (I)
  3. Optional GPIO
GPIO_78 N5 B8 General purpose I/O 78: Options:
  1. Alt 0: Reserved
  2. Alt 1: SEQ_SYNC (B/ open drain)
  3. Optional GPIO
GPIO_77 N4 B8 General purpose I/O 77: Options:
  1. Alt 0: Reserved
  2. Alt 1: EFSYNC (O)/ DASYNC (I)
  3. Optional GPIO
GPIO_76 AD5 B8 General purpose I/O 76: Options:
  1. Alt 0: AWC1_DACD_PWMB_1 (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_75 AC1 B8 General purpose I/O 75: Options:
  1. Alt 0: AWC1_DACS_PWMA_1 (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_74 AC2 B8 General purpose I/O 74: Options:
  1. Alt 0: AWC1_DACD_PWMB_0 (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_73 AC4 B8 General purpose I/O 73: Options:
  1. Alt 0: AWC1_DACS_PWMA_0 (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_72 AC5 B8 General purpose I/O 72: Options:
  1. Alt 0: AWC1_DACCLK_0_1 (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_71 AD1 B8 General purpose I/O 71: Options:
  1. Alt 0: AWC1_OUT_ENZ (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_70 AD2 B8 General purpose I/O 70: Options:
  1. Alt 0: AWC0_DACD_PWMB_1 (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_69 AD3 B8 General purpose I/O 69: Options:
  1. Alt 0: AWC0_DACS_PWMA_1 (O)
  2. Alt 1: MEMAUX_1 (O) (#2)
  3. Optional GPIO
GPIO_68 AD4 B8 General purpose I/O 68: Options:
  1. Alt 0: AWC0_DACD_PWMB_0 (O)
  2. Alt 1: IIC2_SDA (B) (#3)
  3. Optional GPIO
GPIO_67 AF4 B8 General purpose I/O 67: Options:
  1. Alt 0: AWC0_DACS_PWMA_0 (O)
  2. Alt 1: IIC2_SCL (B) (#3)
  3. Optional GPIO
GPIO_66 AE2 B8 General purpose I/O 66: Options:
  1. Alt 0: AWC0_DACCLK_0_1 (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_65 AE3 B8 General purpose I/O 65: Options:
  1. Alt 0: AWC0_OUT_ENZ (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_64 AE4 B8 General purpose I/O 64: Options:
  1. Alt 0: OCLKB (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_63 AG2 B8 General purpose I/O 63: Options:
  1. Alt 0: Reserved
  2. Alt 1: OCLKD (O) (#2)
  3. Optional GPIO
GPIO_62 AG3 B8 General purpose I/O 62: Options:
  1. Alt 0: Reserved
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_61 AF1 B8 General purpose I/O 61: Options:
  1. Alt 0: Reserved
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_60 AF2 B8 General purpose I/O 60: Options:
  1. Alt 0: Reserved
  2. Alt 1: UART2_RXD (I) (#2)
  3. Optional GPIO
GPIO_59 AG1 B8 General purpose I/O 59: Options:
  1. Alt 0: Reserved
  2. Alt 1: UART2_TXD (O) (#2)
  3. Optional GPIO
GPIO_58 V1 B8 General purpose I/O 58: Options:
  1. Alt 0: Reserved
  2. Alt 1: Reserved
  3. Optional GPIO
GPIO_57 V2 B8 General purpose I/O 57: Options:
  1. Alt 0: Reserved
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_56 W2 B8 General purpose I/O 56: Options:
  1. Alt 0: Reserved
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_55 K29 B8 General purpose I/O 55: Options:
  1. Alt 0: Reserved
  2. Alt 1: Reserved
  3. Optional GPIO
GPIO_54 K28 B8 General purpose I/O 54: Options:
  1. Alt 0: Reserved
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_53 W3 B8 General purpose I/O 53: Options:
  1. Alt 0: Reserved
  2. Alt 1: LED_DRIVER_ON (O)
  3. Optional GPIO
GPIO_52 W4 B8 General purpose I/O 52: Options:
  1. Alt 0: Reserved
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_51 V5 B8 General purpose I/O 51: Options:
  1. Alt 0: Reserved
  2. Alt 1: DMD_PWR_EN (O)
  3. Optional GPIO
GPIO_50 AC29 B8 General purpose I/O 50: Options:
  1. Alt 0: SSP0_CSZ_3 (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_49 AC30 B8 General purpose I/O 49: Options:
  1. Alt 0: SSP0_CSZ_4 (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_48 AB26 B8 General purpose I/O 48: Options:
  1. Alt 0: USB OTG External USB Switch Control (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_47 AB28 B8 General purpose I/O 47: Options:
  1. Alt 0: PM_ADDR_23 (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_46 K27 B8 General purpose I/O 46: Options:
  1. Alt 0: Reserved
  2. Alt 1: SSP2_BC_CSZ (O-MST/I-SLV)
  3. Optional GPIO
GPIO_45 J30 B8 General purpose I/O 45: Options:
  1. Alt 0: Reserved
  2. Alt 1: SSP2_CSZ_2 (O-MST/I-SLV)
  3. Optional GPIO
GPIO_44 J29 B8 General purpose I/O 44: Options:
  1. Alt 0: OCLKC (O) (#1)
  2. Alt 1: SSP2_CSZ_1 (O-MST/I-SLV)
  3. Optional GPIO
GPIO_43 J27 B8 General purpose I/O 43: Options:
  1. Alt 0: OCLKD (O) (#1)
  2. Alt 1: SSP2_CSZ_0 (O-MST/I-SLV)
  3. Optional GPIO
GPIO_42 J26 B8 General purpose I/O 42: Options:
  1. Alt 0: IIC2_SDA (B) (#1)
  2. Alt 1: SSP2_DO (O)
  3. Optional GPIO
GPIO_41 H30 B8 General purpose I/O 41: Options:
  1. Alt 0: IIC2_SCL (B) (#1)
  2. Alt 1: SSP2_DI (I)
  3. Optional GPIO
GPIO_40 H29 B8 General purpose I/O 40: Options:
  1. Alt 0: MEMAUX_1 (O) (#1)
  2. Alt 1: SSP2_SCLK (O-MST/I-SLV)
  3. Optional GPIO
GPIO_39 H28 B8 General purpose I/O 39: Options:
  1. Alt 0: UART2_RXD (I) (#1)
  2. Alt 1: HBT_CLKOUT (O)
  3. Optional GPIO
GPIO_38 H27 B8 General purpose I/O 38: Options:
  1. Alt 0: UART2_TXD (O) (#1)
  2. Alt 1: HBT_DO (O)
  3. Optional GPIO
GPIO_37 H26 B8 General purpose I/O 37: Options:
  1. Alt 0: Reserved
  2. Alt 1: DAO_CLKOUT (O)
  3. Optional GPIO
GPIO_36 G30 B8 General purpose I/O 36: Options:
  1. Alt 0: Reserved
  2. Alt 1: DAO_DO_1 (O)
  3. Optional GPIO
GPIO_35 G29 B8 General purpose I/O 35: Options:
  1. Alt 0: OCLKC (O) (#2)
  2. Alt 1: DAO_DO_0 (O)
  3. Optional GPIO
GPIO_34 Y1 B8 General purpose I/O 34: Options:
  1. Alt 0: WRP_CAMERA_TRIG (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_33 Y2 B8 General purpose I/O 33: Options:
  1. Alt 0: PAUX11 (O)
  2. Alt 1: IIC2_SDA (B) (#2)
  3. Optional GPIO
GPIO_32 Y4 B8 General purpose I/O 32: Options:
  1. Alt 0: PAUX10 (O)
  2. Alt 1: IIC2_SCL (B) (#2)
  3. Optional GPIO
GPIO_31 Y5 B8 General purpose I/O 31: Options:
  1. Alt 0: PAUX9 (O)
  2. Alt 1: PAUX_INT3 (O)
  3. Optional GPIO
GPIO_30 AA1 B8 General purpose I/O 30: Options:
  1. Alt 0: PAUX8 (O)
  2. Alt 1: PAUX_INT2 (O)
  3. Optional GPIO
GPIO_29 AA2 B8 General purpose I/O 29: Options:
  1. Alt 0: PAUX7 (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_28 AA3 B8 General purpose I/O 28: Options:
  1. Alt 0: PAUX6 (O)
  2. Alt 1: LEDSEL_4 (O)
  3. Optional GPIO
GPIO_27 AA4 B8 General purpose I/O 27: Options:
  1. Alt 0: PAUX5 (O)
  2. Alt 1: LEDSEL_3 (O)
  3. Optional GPIO
GPIO_26 AA5 B8 General purpose I/O 26: Options:
  1. Alt 0: PAUX4 (O)
  2. Alt 1: LEDSEL_2 (O)
  3. Optional GPIO
GPIO_25 AB2 B8 General purpose I/O 25: Options:
  1. Alt 0: PAUX3 (O)
  2. Alt 1: LEDSEL_1 (O)
  3. Optional GPIO
GPIO_24 AB3 B8 General purpose I/O 24: Options:
  1. Alt 0: PAUX2 (O)
  2. Alt 1: LEDSEL_0 (O)
  3. Optional GPIO
GPIO_23 AB4 B8 General purpose I/O 23: Options:
  1. Alt 0: PAUX1 (O) {SEQ Index}
  2. Alt 1: PAUX_INT1 (O)
  3. Optional GPIO
GPIO_22 AB5 B8 General purpose I/O 22: Options:
  1. Alt 0: PAUX0 (O)
  2. Alt 1: PAUX_INT0 (O)
  3. Optional GPIO
GPIO_21 P3 B8 General purpose I/O 21: Options:
  1. Alt 0: PWM-IN1 (I)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_20 P2 B8 General purpose I/O 20: Options:
  1. Alt 0: PWM-IN0 (I)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_19 P1 B8 General purpose I/O 19: Options:
  1. Alt 0: IR1 (I)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_18 R5 B8 General purpose I/O 18: Options:
  1. Alt 0: IR0 (I)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_17 R4 B8 General purpose I/O 17: Options:
  1. Alt 0: N/A
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_16 R2 B8 General purpose I/O 16: Options:
  1. Alt 0: UART1_RTSZ (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_15 R1 B8 General purpose I/O 15: Options:
  1. Alt 0: UART1_CTSZ (I)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_14 T3 B8 General purpose I/O 14: Options:
  1. Alt 0: UART1_RXD (I)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_13 T4 B8 General purpose I/O 13: Options:
  1. Alt 0: UART1_TXD (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_12 T5 B8 General purpose I/O 12: Options:
  1. Alt 0: IIC1_SDA (B)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_11 T2 B8 General purpose I/O 11: Options:
  1. Alt 0: IIC1_SCL (B)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_10 V3 B8 General purpose I/O 10: Options:
  1. Alt 0: SAS_INTGTR_EN (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_09 U1 B8 General purpose I/O 09: Options:
  1. Alt 0: SAS_CSZ (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_08 U2 B8 General purpose I/O 08: Options:
  1. Alt 0: SAS_DO (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_07 U4 B8 General purpose I/O 07: Options:
  1. Alt 0: SAS_DI (I)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_06 V4 B8 General purpose I/O 06: Options:
  1. Alt 0: SAS_CLK (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_05 A17 B8 General purpose I/O 05: Options:
  1. Alt 0: SSP1_CSZ_2 (O-MST/I-SLV)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_04 B17 B8 General purpose I/O 04: Options:
  1. Alt 0: SSP1_CSZ_1 (O-MST/I-SLV)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_03 B15 B8 General purpose I/O 03: Options:
  1. Alt 0: SSP1_CSZ_0 (O-MST/I-SLV)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_02 C16 B8 General purpose I/O 02: Options:
  1. Alt 0: SSP1_DO (O)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_01 D16 B8 General purpose I/O 01: Options:
  1. Alt 0: SSP1_DI (I)
  2. Alt 1: N/A
  3. Optional GPIO
GPIO_00 E16 B8 General purpose I/O 00: Options:
  1. Alt 0: SSP1_SCLK (O-MST/I-SLV)
  2. Alt 1: N/A
  3. Optional GPIO
See Table 5-13 for more information on I/O definitions.
This table defines the GPIO capabilities of the DLPC6540. Please see Section 7.3.6 for specific product configuration allocations of these GPIO.
Most GPIO have at least one alternate hardware functional use in addition to being available as a general purpose I/O. Depending on the product configuration, GPIO may be reserved specifically for use as an alternate hardware function (and would therefore not be available as a general purpose I/O). More information on GPIO allocations for specific product configurations can be found in Section 7.3.6.
All GPIO that are available as a general purpose I/O must be configured as an input, a standard output, or an open-drain output. This is set in the flash configuration. Configure unused GPIO as a logic zero output and leave unconnected, otherwise an external pullup or pulldown resistor is required to avoid a floating input. The reset default for all GPIO is as an input signal.
An external pullup resistor (≤ 10 kΩ) is required for each signal configured as open-drain output.
Table 5-11 Clock and Support
PIN TYPE(1) DESCRIPTION
NAME NO.
REFCLKA_I AJ18 I9 Crystal A Input: Reference clock crystal input(2)(3)
REFCLKA_O AK18 O10 Crystal A Output: Reference clock crystal output(2)
REFCLKB_I B16 I14 Crystal B Input: Reference clock crystal input(2)(3)
REFCLKB_O A16 O15 Crystal B Output: Reference clock crystal output(2)
OCLKA AD30 O8 General Purpose Output Clock A (4)
Targeted for driving Color Wheel motor controller. Frequency is software programmable, with a power-up default frequency of 0.77 MHz.
Note: The output frequency is not affected by non-power-up reset operations (that is, the system holds the last programmed value until system is power cycled).
See Table 5-13 for more information on I/O definitions.
For more information on this signal see Section 6.11.
For applications where an external oscillator is used in place of a crystal, use an oscillator to drive this pin.
For more information on this signal see Section 6.19.
Table 5-12 Power and Ground
PIN TYPE(1) DESCRIPTION
NAME NO.
VDD115_PLLMA AE18 PWR 1.15-V digital power for MCG (Master Clock Generator A) PLL
VDD115_PLLMB F15 PWR 1.15-V digital power for MCG (Master Clock Generator B) PLL
VAD115_PLLS F16 PWR 1.15-V analog power for SCG doubler PLL
VAD18_PLLMA AE19 PWR 1.8-V analog power for MCG (Master Clock Generator A) PLL
VAD18_PLLMB F14 PWR 1.8-V analog power for MCG (Master Clock Generator B) PLL
VAD33_OSCA Y18 PWR 3.3-V analog power for Crystal-OSC
VAD33_OSCB L17 PWR 3.3-V analog power for Crystal-OSC
VAD115_FPD F7,F9,F11,J6,L12 PWR 1.15-V analog power for FPD
VDD33_FPD E6,E8,E10,E12,E14,G6,L11,L13 PWR 3.3-V digital power for FPD
VAD115_VX1 F24,L18 PWR 1.15-V analog power for VX1
VAD18_VX1 E18,L19 PWR 1.8-V analog power for VX1
VAD33_USB D27,E26,F25 PWR 3.3-V analog power for USB
VDD18_SCS L16,R6,T25,AE16 PWR 1.8-V digital power for SCS DRAM
VDD121_SCS L15,N11,P20,U11,V20,Y16 PWR 1.21-V digital power for SCS SRAM
VAD115_HSSI Y14,Y19,AF7,AF9,AF11,AF13AF21,AF23,AF25 PWR 1.15-V analog power for HSSI interface
VAD115_HSSI0_PLL AE22 PWR 1.15-V analog power for HSSI-0 PLL
VAD115_HSSI1_PLL AE10 PWR 1.15-V analog power for HSSI-1 PLL
VDD33_HSSI Y12,Y20,AE8,AE12,AE20,AE24 PWR 3.3-V digital power for HSSI interface
VAD18_LSIF Y15,AE13,AE14 PWR 1.8-V analog power for DMD low-speed interface
LVDS_VREFTEST AF16 Manufacturing test use only; must be left open-unconnected
VDD115 L14,L20,M11,N20,P11,R20,T11,U20,V11,W20,Y11,Y13,Y17 PWR 1.15-V core power
VDD33 H25,K25,L6,M20,M25,N6,P25,R11,T20,U6,V25,W6,W11,Y25,AA6,AB25,AC6,AD25,AE6 PWR 3.3-V digital power
VSS A1,A2,A3,A5,A7,A9,A11,A13,A15,A18,A20,A22,A24,A26,A28,A30,B1,B2,B3,B5,B7,B9,B11,B13,B18,B20,B22,B24,B26,B28,B30,C3,C4,C6,C8,C10,C12,C14,C17,C19,C21,C23,C25,C29,D1,D2,D6,D8,D10,D12,D14,D17,D19,D21,D23,D25,D28,E3,E4,E5,E7,E9,E11,E13,E15,E22,E25,E28,F1,F2,F5,F6,F8,F10,F12,F13,F17,F18,F20,F30,G3,G4,G5,G27,H1,H2,H5,H6,J3,J4,J5,J25.J28,K6,K30,L1,L25,L27,M3,M6,(M12),(M13),(M14),(M15),(M16),(M17),(M18),(M19),N1,(N12,(N13),(N14),(N15),(N16),(N17),(N18),(N19),N25,N28,P6,(P12),(P13),(P14),(P15),(P16),(P17),(P18),(P19),P30,R3,(R12),(R13),(R14),(R15),(R16),(R17),(R18),(R19),R25,R27,T1,T6,(T12),(T13),(T14),(T15),(T16),(T17),(T18),(T19),U3,U5,(U12),(U13),(U14),(U15),(U16),(U17),(U18),(U19),U25,U28,V6,(V12),(V13),(V14),(V15),(V16),(V17),(V18),(V19),V30,W1,W5,(W12),(W13),(W14),(W15),(W16),(W17),(W18),(W19),W25,W27,Y3,Y6,AA25,AA28,AB1,AB6,AB30,AC3,AC25,AC27,AD6,AE1,AE5,AE7,AE9,AE11,AE15,AE17,AE21,AE23,AE25,AE26,AE28,AF3,AF5,AF6,AF8,AF10,AF12,AF14,AF15,AF17,AF18,AF19,AF20,AF22,AF24,AF26,AF28,AF30,AG4,AG6,AG8,AG10,AG12,AG14,AG16,AG18,AG23,AG25,AG27,AG29,AH1,AH2,AH3,AH4,AH6,AH8,AH10,AH12,AH14,AH16,AH18,AH21,AH23,AH25,AH27,AH29,AH30,AJ1,AJ3,AJ5,AJ7,AJ9,AJ11,AJ13,AJ15,AJ17,AJ22,AJ24,AJ26,AJ28,AJ30,AK1,AK3,AK5,AK7,AK9,AK11,AK13,AK15,AK17,AK22,AK24,AK26,AK28,AK30 RTN GND for all power supplies. Ball numbers in parenthesis are also used as thermal balls and are located within the package center region.
VPGM G25 Manufacturing use only (efuse); must be tied to ground
See Table 5-13 for more information on I/O definitions.
Table 5-13 I/O Type Subscript Definition
TYPE SUPPLY REFERENCE ESD STRUCTURE
SUBSCRIPT DESCRIPTION
1 1.8 V SERDES (VX1) VAD18_VX1 ESD diode to supply rail and GND
2 1.8-V LVDS (LS DMD) VAD18_LSIF ESD diode to supply rail and GND
3 1.8-V LMCMOS (LS DMD) VAD18_LSIF ESD diode to supply rail and GND
4 3.3-V OpenDrain (VX1) VDD33 ESD diode to supply rail and GND
5 3.3-V LVDS (FPD) VDD33_FPD ESD diode to supply rail and GND
6 3.3-V LVCMOS (PP) VDD33_FPD ESD diode to supply rail and GND
7 1.15-V HSSI (HS DMD) VAD115_HSSI ESD diode to supply rail and GND
8 3.3-V LVCMOS I/O (8ma output drive - GPIO, etc. ) VDD33 ESD diode to supply rail and GND
9 3.3-V LVCMOS I/O (OSC) VAD33_OSCA ESD diode to GND
10 3.3-V LVCMOS I/O (OSC) VAD33_OSCA ESD diode to supply rail and GND
11 3.3-V USB (USB) VAD33_USB ESD diode and LBJT to GND
12 3.3-V LVCMOS (USB) VAD33_USB ESD diode to supply rail and GND
13 3.3-V OpenDrain (I2C) VDD33 ESD diode to supply rail and GND
14 3.3-V LVCMOS I/O (OSC) VAD33_OSCB ESD diode to GND
15 3.3-V LVCMOS I/O (OSC) VAD33_OSCB ESD diode to supply rail and GND
TYPE
I Input N/A
O Output
B Bidirectional
PWR Power
RTN Ground return
Table 5-14 Internal Pullup and Pulldown Characteristics(1)
INTERNAL PULLUP AND PULLDOWN
RESISTOR CHARACTERISTICS
CONDITIONS MIN MAX UNIT
Weak pullup resistance VIN = 0.8 V, VDD33 = 3.3 V 19 50
VIN = 2.0 V, VDD33 = 3.3 V 12 39
An external 5.7-kΩ or less pullup or pulldown resistor (if needed) is sufficient for any voltage condition to correctly override any associated internal pullup or pulldown resistance.