JAJSON9 May   2022 DP83TC813R-Q1 , DP83TC813S-Q1

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Diagnostic Tool Kit
        1. 8.3.1.1 Signal Quality Indicator
        2. 8.3.1.2 Electrostatic Discharge Sensing
        3. 8.3.1.3 Time Domain Reflectometry
        4. 8.3.1.4 Voltage Sensing
        5. 8.3.1.5 BIST and Loopback Modes
          1. 8.3.1.5.1 Data Generator and Checker
          2. 8.3.1.5.2 xMII Loopback
          3. 8.3.1.5.3 PCS Loopback
          4. 8.3.1.5.4 Digital Loopback
          5. 8.3.1.5.5 Analog Loopback
          6. 8.3.1.5.6 Reverse Loopback
      2. 8.3.2 Compliance Test Modes
        1. 8.3.2.1 Test Mode 1
        2. 8.3.2.2 Test Mode 2
        3. 8.3.2.3 Test Mode 4
        4. 8.3.2.4 Test Mode 5
    4. 8.4 Device Functional Modes
      1. 8.4.1  Power Down
      2. 8.4.2  Reset
      3. 8.4.3  Standby
      4. 8.4.4  Normal
      5. 8.4.5  Sleep Ack
      6. 8.4.6  Sleep Request
      7. 8.4.7  Sleep Fail
      8. 8.4.8  Sleep
      9. 8.4.9  Wake-Up
      10. 8.4.10 TC10 System Example
      11. 8.4.11 Media Dependent Interface
        1. 8.4.11.1 100BASE-T1 Master and 100BASE-T1 Slave Configuration
        2. 8.4.11.2 Auto-Polarity Detection and Correction
        3. 8.4.11.3 Jabber Detection
        4. 8.4.11.4 Interleave Detection
      12. 8.4.12 MAC Interfaces
        1. 8.4.12.1 Media Independent Interface
        2. 8.4.12.2 Reduced Media Independent Interface
        3. 8.4.12.3 Reduced Gigabit Media Independent Interface
        4. 8.4.12.4 Serial Gigabit Media Independent Interface
      13. 8.4.13 Serial Management Interface
      14. 8.4.14 Direct Register Access
      15. 8.4.15 Extended Register Space Access
      16. 8.4.16 Write Address Operation
        1. 8.4.16.1 MMD1 - Write Address Operation
      17. 8.4.17 Read Address Operation
        1. 8.4.17.1 MMD1 - Read Address Operation
      18. 8.4.18 Write Operation (No Post Increment)
        1. 8.4.18.1 MMD1 - Write Operation (No Post Increment)
      19. 8.4.19 Read Operation (No Post Increment)
        1. 8.4.19.1 MMD1 - Read Operation (No Post Increment)
      20. 8.4.20 Write Operation (Post Increment)
        1. 8.4.20.1 MMD1 - Write Operation (Post Increment)
      21. 8.4.21 Read Operation (Post Increment)
        1. 8.4.21.1 MMD1 - Read Operation (Post Increment)
    5. 8.5 Programming
      1. 8.5.1 Strap Configuration
      2. 8.5.2 LED Configuration
      3. 8.5.3 PHY Address Configuration
    6. 8.6 Register Maps
      1. 8.6.1 Register Access Summary
      2. 8.6.2 DP83TC813 Registers
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Physical Medium Attachment
          1. 9.2.1.1.1 Common-Mode Choke Recommendations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Signal Traces
      2. 11.1.2 Return Path
      3. 11.1.3 Metal Pour
      4. 11.1.4 PCB Layer Stacking
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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サーマルパッド・メカニカル・データ
発注情報

DP83TC813 Registers

Table 8-25 lists the memory-mapped registers for the DP83TC813 registers. All register offset addresses not listed in Table 8-25 must be considered as reserved locations and the register contents must not be modified.

Table 8-25 DP83TC813 Registers
AddressAcronymRegister NameSection
0hBMCR#DP83TC813_DP83TC813_DP83TC813_BMCR
1hBMSR#DP83TC813_DP83TC813_DP83TC813_BMSR
2hPHYIDR1#DP83TC813_DP83TC813_DP83TC813_PHYIDR1
3hPHYIDR2#DP83TC813_DP83TC813_DP83TC813_PHYIDR2
10hPHYSTS#DP83TC813_DP83TC813_DP83TC813_PHYSTS
11hPHYSCR#DP83TC813_DP83TC813_DP83TC813_PHYSCR
12hMISR1#DP83TC813_DP83TC813_DP83TC813_MISR1
13hMISR2#DP83TC813_DP83TC813_DP83TC813_MISR2
15hRECR#DP83TC813_DP83TC813_DP83TC813_RECR
16hBISCR#DP83TC813_DP83TC813_DP83TC813_BISCR
18hMISR3#DP83TC813_DP83TC813_DP83TC813_MISR3
19hREG_19#DP83TC813_DP83TC813_DP83TC813_REG_19
1BhTC10_ABORT_REG#DP83TC813_DP83TC813_DP83TC813_TC10_ABORT_REG
1EhCDCR#DP83TC813_DP83TC813_DP83TC813_CDCR
1FhPHYRCR#DP83TC813_DP83TC813_DP83TC813_PHYRCR
41hRegister_41#DP83TC813_DP83TC813_DP83TC813_REGISTER_41
133hRegister_133#DP83TC813_DP83TC813_DP83TC813_REGISTER_133
17FhRegister_17F#DP83TC813_DP83TC813_DP83TC813_REGISTER_17F
180hRegister_180#DP83TC813_DP83TC813_DP83TC813_REGISTER_180
181hRegister_181#DP83TC813_DP83TC813_DP83TC813_REGISTER_181
182hRegister_182#DP83TC813_DP83TC813_DP83TC813_REGISTER_182
183hLPS_CFG4#DP83TC813_DP83TC813_DP83TC813_LPS_CFG4
184hLPS_CFG#DP83TC813_DP83TC813_DP83TC813_LPS_CFG
185hLPS_CFG5#DP83TC813_DP83TC813_DP83TC813_LPS_CFG5
187hLPS_CFG7#DP83TC813_DP83TC813_DP83TC813_LPS_CFG7
188hLPS_CFG8#DP83TC813_DP83TC813_DP83TC813_LPS_CFG8
189hLPS_CFG9#DP83TC813_DP83TC813_DP83TC813_LPS_CFG9
18AhLPS_CFG10#DP83TC813_DP83TC813_DP83TC813_LPS_CFG10
18ChLPS_CFG3#DP83TC813_DP83TC813_DP83TC813_LPS_CFG3
18EhLPS_STATUS#DP83TC813_DP83TC813_DP83TC813_LPS_STATUS
300hTDR_TX_CFG#DP83TC813_DP83TC813_DP83TC813_TDR_TX_CFG
301hTAP_PROCESS_CFG#DP83TC813_DP83TC813_DP83TC813_TAP_PROCESS_CFG
302hTDR_CFG1#DP83TC813_DP83TC813_DP83TC813_TDR_CFG1
303hTDR_CFG2#DP83TC813_DP83TC813_DP83TC813_TDR_CFG2
304hTDR_CFG3#DP83TC813_DP83TC813_DP83TC813_TDR_CFG3
305hTDR_CFG4#DP83TC813_DP83TC813_DP83TC813_TDR_CFG4
306hTDR_CFG5#DP83TC813_DP83TC813_DP83TC813_TDR_CFG5
310hTDR_TC1#DP83TC813_DP83TC813_DP83TC813_TDR_TC1
430hA2D_REG_48#DP83TC813_DP83TC813_DP83TC813_A2D_REG_48
450hLEDS_CFG_1#DP83TC813_DP83TC813_DP83TC813_LEDS_CFG_1
451hLEDS_CFG_2#DP83TC813_DP83TC813_DP83TC813_LEDS_CFG_2
452hIO_MUX_CFG_1#DP83TC813_DP83TC813_DP83TC813_IO_MUX_CFG_1
453hIO_MUX_CFG_2#DP83TC813_DP83TC813_DP83TC813_IO_MUX_CFG_2
456hIO_MUX_CFG#DP83TC813_DP83TC813_DP83TC813_IO_MUX_CFG
457hIO_STATUS_1#DP83TC813_DP83TC813_DP83TC813_IO_STATUS_1
458hIO_STATUS_2#DP83TC813_DP83TC813_DP83TC813_IO_STATUS_2
45DhCHIP_SOR_1#DP83TC813_DP83TC813_DP83TC813_CHIP_SOR_1
45FhLED1_CLKOUT_ANA_CTRL#DP83TC813_DP83TC813_DP83TC813_LED1_CLKOUT_ANA_CTRL
485hPCS_CTRL_1#DP83TC813_DP83TC813_DP83TC813_PCS_CTRL_1
486hPCS_CTRL_2#DP83TC813_DP83TC813_DP83TC813_PCS_CTRL_2
489hTX_INTER_CFG#DP83TC813_DP83TC813_DP83TC813_TX_INTER_CFG
496hJABBER_CFG#DP83TC813_DP83TC813_DP83TC813_JABBER_CFG
497hTEST_MODE_CTRL#DP83TC813_DP83TC813_DP83TC813_TEST_MODE_CTRL
4A0hRXF_CFG#DP83TC813_DP83TC813_DP83TC813_RXF_CFG
553hPG_REG_4#DP83TC813_DP83TC813_DP83TC813_PG_REG_4
560hTC1_CFG_RW#DP83TC813_DP83TC813_DP83TC813_TC1_CFG_RW
561hTC1_LINK_FAIL_LOSS#DP83TC813_DP83TC813_DP83TC813_TC1_LINK_FAIL_LOSS
562hTC1_LINK_TRAINING_TIME#DP83TC813_DP83TC813_DP83TC813_TC1_LINK_TRAINING_TIME
600hRGMII_CTRL#DP83TC813_DP83TC813_DP83TC813_RGMII_CTRL
601hRGMII_FIFO_STATUS#DP83TC813_DP83TC813_DP83TC813_RGMII_FIFO_STATUS
602hRGMII_CLK_SHIFT_CTRL#DP83TC813_DP83TC813_DP83TC813_RGMII_CLK_SHIFT_CTRL
603hRGMII_EEE_CTRL#DP83TC813_DP83TC813_DP83TC813_RGMII_EEE_CTRL
608hSGMII_CTRL_1#DP83TC813_DP83TC813_DP83TC813_SGMII_CTRL_1
609hSGMII_EEE_CTRL_1#DP83TC813_DP83TC813_DP83TC813_SGMII_EEE_CTRL_1
60AhSGMII_STATUS#DP83TC813_DP83TC813_DP83TC813_SGMII_STATUS
60BhSGMII_EEE_CTRL_2#DP83TC813_DP83TC813_DP83TC813_SGMII_EEE_CTRL_2
60ChSGMII_CTRL_2#DP83TC813_DP83TC813_DP83TC813_SGMII_CTRL_2
60DhSGMII_FIFO_STATUS#DP83TC813_DP83TC813_DP83TC813_SGMII_FIFO_STATUS
618hPRBS_STATUS_1#DP83TC813_DP83TC813_DP83TC813_PRBS_STATUS_1
619hPRBS_CTRL_1#DP83TC813_DP83TC813_DP83TC813_PRBS_CTRL_1
61AhPRBS_CTRL_2#DP83TC813_DP83TC813_DP83TC813_PRBS_CTRL_2
61BhPRBS_CTRL_3#DP83TC813_DP83TC813_DP83TC813_PRBS_CTRL_3
61ChPRBS_STATUS_2#DP83TC813_DP83TC813_DP83TC813_PRBS_STATUS_2
61DhPRBS_STATUS_3#DP83TC813_DP83TC813_DP83TC813_PRBS_STATUS_3
61EhPRBS_STATUS_4#DP83TC813_DP83TC813_DP83TC813_PRBS_STATUS_4
620hPRBS_STATUS_5#DP83TC813_DP83TC813_DP83TC813_PRBS_STATUS_5
622hPRBS_STATUS_6#DP83TC813_DP83TC813_DP83TC813_PRBS_STATUS_6
623hPRBS_STATUS_7#DP83TC813_DP83TC813_DP83TC813_PRBS_STATUS_7
624hPRBS_CTRL_4#DP83TC813_DP83TC813_DP83TC813_PRBS_CTRL_4
625hPATTERN_CTRL_1#DP83TC813_DP83TC813_DP83TC813_PATTERN_CTRL_1
626hPATTERN_CTRL_2#DP83TC813_DP83TC813_DP83TC813_PATTERN_CTRL_2
627hPATTERN_CTRL_3#DP83TC813_DP83TC813_DP83TC813_PATTERN_CTRL_3
628hPMATCH_CTRL_1#DP83TC813_DP83TC813_DP83TC813_PMATCH_CTRL_1
629hPMATCH_CTRL_2#DP83TC813_DP83TC813_DP83TC813_PMATCH_CTRL_2
62AhPMATCH_CTRL_3#DP83TC813_DP83TC813_DP83TC813_PMATCH_CTRL_3
639hTX_PKT_CNT_1#DP83TC813_DP83TC813_DP83TC813_TX_PKT_CNT_1
63AhTX_PKT_CNT_2#DP83TC813_DP83TC813_DP83TC813_TX_PKT_CNT_2
63BhTX_PKT_CNT_3#DP83TC813_DP83TC813_DP83TC813_TX_PKT_CNT_3
63ChRX_PKT_CNT_1#DP83TC813_DP83TC813_DP83TC813_RX_PKT_CNT_1
63DhRX_PKT_CNT_2#DP83TC813_DP83TC813_DP83TC813_RX_PKT_CNT_2
63EhRX_PKT_CNT_3#DP83TC813_DP83TC813_DP83TC813_RX_PKT_CNT_3
648hRMII_CTRL_1#DP83TC813_DP83TC813_DP83TC813_RMII_CTRL_1
649hRMII_STATUS_1#DP83TC813_DP83TC813_DP83TC813_RMII_STATUS_1
64AhRMII_OVERRIDE_CTRL#DP83TC813_DP83TC813_DP83TC813_RMII_OVERRIDE_CTRL
871hdsp_reg_71#DP83TC813_DP83TC813_DP83TC813_DSP_REG_71
1000hMMD1_PMA_CTRL_1#DP83TC813_DP83TC813_DP83TC813_MMD1_PMA_CTRL_1
1001hMMD1_PMA_STATUS_1#DP83TC813_DP83TC813_DP83TC813_MMD1_PMA_STATUS_1
1007hMMD1_PMA_STAUS_2#DP83TC813_DP83TC813_DP83TC813_MMD1_PMA_STAUS_2
100BhMMD1_PMA_EXT_ABILITY_1#DP83TC813_DP83TC813_DP83TC813_MMD1_PMA_EXT_ABILITY_1
1012hMMD1_PMA_EXT_ABILITY_2#DP83TC813_DP83TC813_DP83TC813_MMD1_PMA_EXT_ABILITY_2
1834hMMD1_PMA_CTRL_2#DP83TC813_DP83TC813_DP83TC813_MMD1_PMA_CTRL_2
1836hMMD1_PMA_TEST_MODE_CTRL#DP83TC813_DP83TC813_DP83TC813_MMD1_PMA_TEST_MODE_CTRL
3000hMMD3_PCS_CTRL_1#DP83TC813_DP83TC813_DP83TC813_MMD3_PCS_CTRL_1
3001hMMD3_PCS_Status_1#DP83TC813_DP83TC813_DP83TC813_MMD3_PCS_STATUS_1

Complex bit access types are encoded to fit into small table cells. Table 8-26 shows the codes that are used for access types in this section.

Table 8-26 DP83TC813 Access Type Codes
Access TypeCodeDescription
Read Type
HHSet or cleared by hardware
RRRead
RHR
H
Read
Set or cleared by hardware
Write Type
WWWrite
W0SW
0S
Write
0 to set
W1SW
1S
Write
1 to set
WSCWWrite
Reset or Default Value
-nValue after reset or the default value

8.6.2.1 BMCR Register (Address = 0h) [Reset = 2100h]

BMCR is shown in Figure 8-20 and described in Table 8-27.

Return to the Summary Table.

Figure 8-20 BMCR Register
15141312111098
MII_reset xMII Loopback Manual_speed_MIIAuto-Negotiation EnablePower DownIsolateRESERVEDDuplex Mode
RH/W1S-0bR/W-0bR-1bR-0bR/W-0bR/W-0bR-0bR-1b
76543210
RESERVEDRESERVED
R/W-0bR-0b
Table 8-27 BMCR Register Field Descriptions
BitFieldTypeResetDescription
15MII_reset RH/W1S0b MII Reset. This bit will reset the Digital blocks of the PHY and return registers 0x0-0x0F back to default values. Other register will not be affected.
0b = No reset
1b = Digital in reset and all MII regs (0x0 - 0xF) reset to default
14xMII Loopback R/W0b xMII Loopback: 1 = xMII Loopback enabled 0 = Normal Operation When xMII loopback mode is activated, the transmitted data presented on xMII TXD is looped back to xMII RXD internally. There is no LINK indication generated when xMII loopback is enabled.
1b = Enable Loopback from G/MII input to G/MII output
13Manual_speed_MIIR1b Speed Selection: Always 100-Mbps Speed
12Auto-Negotiation EnableR0b Auto-Negotiation: Not supported on this device
0b = Disable Auto-Negotiation
11Power DownR/W0b Power Down: The PHY is powered down after this bit is set. Only register access is enabled during this power down condition.
The power down mode can be controlled via this bit or via INT_N pin. INT_N pin needs to be configured to operate as power down control. This bit is OR-ed with the input from the INT_N pin. When the active low INT_N is asserted, this bit is set.
0b = Normal Mode
1b = IEEE Power Down
10IsolateR/W0b Isolate:Isolates the port from the xMII with the exception of the serial management interface
0b = Normal Mode
1b = Enable Isolate Mode
9RESERVEDR0b Reserved
8Duplex ModeR1b 1 = Full Duplex 0 = Half duplex
0b = Half duplex
1b = Full Duplex
7RESERVEDR/W0b Reserved
6-0RESERVEDR0b Reserved

8.6.2.2 BMSR Register (Address = 1h) [Reset = 0061h]

BMSR is shown in Figure 8-21 and described in Table 8-28.

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Figure 8-21 BMSR Register
15141312111098
100Base-T4100Base-X Full Duplex100Base-X Half Duplex10 Mbps Full Duplex10 Mbps Half DuplexRESERVED
R-0bR-0bR-0bR-0bR-0bR-0b
76543210
RESERVEDMF Preamble SuppressionAuto-Negotiation CompleteRemote faultAuto-Negotiation AbilityLink statusjabber detectExtended Capability
R-0bR-1bR-1bH-0bR-0b0bH-0bR-1b
Table 8-28 BMSR Register Field Descriptions
BitFieldTypeResetDescription
15100Base-T4R0b Always 0 - PHY not able to perform 100Base-T4
14100Base-X Full DuplexR0b 1 = PHY able to perform full duplex 100Base-X 0 = PHY not able to perform full duplex 100Base-X
0b = PHY not able to perform full duplex 100Base-X
1b = PHY able to perform full duplex 100Base-X
13100Base-X Half DuplexR0b 1 = PHY able to perform half duplex 100Base-X 0 = PHY not able to perform half duplex 100Base-X
0b = PHY not able to perform half duplex 100Base-X
1b = PHY able to perform half duplex 100Base-X
1210 Mbps Full DuplexR0b 1 = PHY able to operate at 10Mbps in full duplex 0 = PHY not able to operate at 10Mbps in full duplex
0b = PHY not able to operate at 10Mbps in full duplex
1b = PHY able to operate at 10Mbps in full duplex
1110 Mbps Half DuplexR0b 1 = PHY able to operate at 10Mbps in half duplex 0 = PHY not able to operate at 10Mbps in half duplex
0b = PHY not able to operate at 10Mbps in half duplex
1b = PHY able to operate at 10Mbps in half duplex
10-7RESERVEDR0b Reserved
6MF Preamble SuppressionR1b 1 = PHY will accept management frames with preamble suppressed 0 = PHY will not accept management frames with preamble suppressed
0b = PHY will not accept management frames with preamble suppressed
1b = PHY will accept management frames with preamble suppressed
5Auto-Negotiation CompleteR1b 1 = Auto-Negotiation process completed 0 = Auto Negotiation process not completed (either still in process, disabled or reset)
0b = Auto Negotiation process not completed (either still in process, disabled or reset)
1b = Auto-Negotiation process completed
4Remote faultH0b 1 = Remote fault condition detected 0 = No remote fault condition detected
0b = No remote fault condition detected
1b = Remote fault condition detected
3Auto-Negotiation AbilityR0b 1 = PHY is able to perform Auto-Negotiation 0 = PHY is not able to perform Auto-Negotiation
0b = PHY is not able to perform Auto-Negotiation
1b = PHY is able to perform Auto-Negotiation
1jabber detectH0b 1= jabber condition detected 0 = No jabber condition detected
0b = No jabber condition detected
1b = jabber condition detected
0Extended CapabilityR1b 1 = Extended register capabilities 0 = Basic register set capabilities only
0b = Basic register set capabilities only
1b = Extended register capabilities

8.6.2.3 PHYIDR1 Register (Address = 2h) [Reset = 2000h]

PHYIDR1 is shown in Figure 8-22 and described in Table 8-29.

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Figure 8-22 PHYIDR1 Register
15141312111098
Organizationally Unique Identifier Bits 21:6
R-10000000000000b
76543210
Organizationally Unique Identifier Bits 21:6
R-10000000000000b
Table 8-29 PHYIDR1 Register Field Descriptions
BitFieldTypeResetDescription
15-0Organizationally Unique Identifier Bits 21:6R10000000000000b Organizationally Unique Identification Number

8.6.2.4 PHYIDR2 Register (Address = 3h) [Reset = A211h]

PHYIDR2 is shown in Figure 8-23 and described in Table 8-30.

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Figure 8-23 PHYIDR2 Register
15141312111098
Organizationally Unique Identifier Bits 5:0Model Number
R-101000bR-100001b
76543210
Model NumberRevision Number
R-100001bR-1b
Table 8-30 PHYIDR2 Register Field Descriptions
BitFieldTypeResetDescription
15-10Organizationally Unique Identifier Bits 5:0R101000b Organizationally Unique Identification Number
9-4Model NumberR100001b Vendor Model Number: The six bits of vendor model number are mapped from bits 9 to 4
3-0Revision NumberR1b Device Revision Number
0b = Silicon Rev 1.0
1b = Silicon Rev 2.0

8.6.2.5 PHYSTS Register (Address = 10h) [Reset = 0004h]

PHYSTS is shown in Figure 8-24 and described in Table 8-31.

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Figure 8-24 PHYSTS Register
15141312111098
RESERVEDRESERVEDreceive_error_latchRESERVEDRESERVEDsignal_detectdescrambler_lockRESERVED
R-0bR-0bH-0bH-0bH-0bR/W0S-0bR/W0S-0bR-0b
76543210
mii_interruptRESERVEDjabber_dtctRESERVEDloopback_statusduplex_statusRESERVEDlink_status
H-0bR-0bR-0bH-0bR-0bR-1bR-0bR-0b
Table 8-31 PHYSTS Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0b Reserved
14RESERVEDR0b Reserved
13receive_error_latchH0b RxerrCnt0 since last read.clear on read
12RESERVEDH0b Reserved
11RESERVEDH0b Reserved
10signal_detectR/W0S0b Channel ok latch low
0b = Channel ok had been reset
1b = Channel ok is set
9descrambler_lockR/W0S0b Descrambler lock latch low
0b = Descrmabler had been locked
1b = Descrambler is locked
8RESERVEDR0b Reserved
7mii_interruptH0b Interrupts pin status, cleared on reading 0x12 1b0 = Interrupts pin not set 1b1 = Interrupt pin had been set
6RESERVEDR0b Reserved
5jabber_dtctR0b duplicate from reg.0x1.1
4RESERVEDH0b Reserved
3loopback_statusR0b MII loopback status
0b = No MII loopback
1b = MII loopback
2duplex_statusR1b Duplex mode status
0b = Half duplex
1b = Full duplex
1RESERVEDR0b Reserved

8.6.2.6 PHYSCR Register (Address = 11h) [Reset = 010Bh]

PHYSCR is shown in Figure 8-25 and described in Table 8-32.

Return to the Summary Table.

Figure 8-25 PHYSCR Register
15141312111098
dis_clk_125pwr_save_mode_enpwr_save_modesgmii_soft_resetuse_PHYAD0_as_Isolatetx_fifo_depth
R/W-0bR/W-0bR/W-0bR/WSC-0bR/W-0bR/W-1b
76543210
RESERVEDRESERVEDint_polforce_interruptINTENINT_OE
R/W-0bR-0bR/W-1bR/W-0bR/W-1bR/W-1b
Table 8-32 PHYSCR Register Field Descriptions
BitFieldTypeResetDescription
15dis_clk_125R/W0b 1 = Disable CLK125 (Sourced by the CLK125 port)
1b = Disable CLK125 (Sourced by the CLK125 port)
14pwr_save_mode_enR/W0b Enable power save mode config from reg
13-12pwr_save_modeR/W0b Power Save Mode
0b = Normal mode
1b = IEEE mode: power down all digital and analog blocks, if bit [11] set to zero, PLL is also powered down 10 = Reserved 11 = Reserved
11sgmii_soft_resetR/WSC0b Reset SGMII
10use_PHYAD0_as_IsolateR/W0b 1- when phy_addr == 0, isolate MAC Interface 0- do not Isolate for PHYAD == 0.
0b = do not Isolate for PHYAD is 0.
1b = when phy_addr is 0, isolate MAC Interface
9-8tx_fifo_depthR/W1b RMII TX fifo depth
0b = 4 nibbles
1b = 5 nibbles
1010b = 6 nibbles
1011b = 8 nibbles
7RESERVEDR/W0b Reserved
6-4RESERVEDR0b Reserved
3int_polR/W1b Interrupt Polarity
0b = Steady state (normal operation) without an interrupt is logical 0; during interrupt, pin is logical 1
1b = Steady state (normal operation) without an interrupt is logical 1; during interrupt, pin is logical 0
2force_interruptR/W0b Force interrupt pin
0b = Do not force interrupt pin
1b = Force interrupt pin
1INTENR/W1b Enable interrupts
0b = Disable interrupts
1b = Enable interrupts
0INT_OER/W1b Interrupt/Power down pin configuration
0b = PIN is a power down PIN (input)
1b = PIN is an interrupt pin (output)

8.6.2.7 MISR1 Register (Address = 12h) [Reset = 0000h]

MISR1 is shown in Figure 8-26 and described in Table 8-33.

Return to the Summary Table.

Figure 8-26 MISR1 Register
15141312111098
link_qual_intenergy_det_intlink_intwol_intesd_intms_train_done_intfhf_intrhf_int
H-0bH-0bH-0bH-0bH-0bH-0bH-0bH-0b
76543210
link_qual_int_enenergy_det_int_enlink_int_enwol_int_enesd_int_enms_train_done_int_enfhf_int_enrhf_int_en
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 8-33 MISR1 Register Field Descriptions
BitFieldTypeResetDescription
14energy_det_intH0b This INT can be asserted upon Rising edge only of energy_det signal using reg0x101 bit [0] : cfg_energy_det_int_le_only. status output of energy_det_hist signal on reg0x19 bit[10].
0b = No Change of energy detected
1b = Change of energy_detected (both rising and falling edges)
12wol_intH0b Interrupt bit indicating that WOL packet is received
0b = No WoL interrupt pending.
1b = WoL packet received interrupt is pending and is cleared by the current read.
11esd_intH0b 1 = ESD detected interrupt is pending and is cleared by the current read. 0 = No ESD interrupt pending.
10ms_train_done_intH0b 1 = M/S Link Training Completed interrupt is pending and is cleared by the current read. 0 = No M/S Link Training Completed interrupt pending.
9fhf_intH0b 1 = False carrier counter half-full interrupt is pending and is cleared by the current read. 0 = No false carrier counter half-full interrupt pending.
8rhf_intH0b 1 = Receive error counter half-full interrupt is pending and is cleared by the current read. 0 = No receive error carrier counter half-full interrupt pending.
6energy_det_int_enR/W0b Enable Interrupt on change of Energy Detect histr. Status
4wol_int_enR/W0b Enable Interrupt on WoL detection
3esd_int_enR/W0b Enable Interrupt on ESD detect event
2ms_train_done_int_enR/W0b Enable Interrupt on M/S Link Training Completed event
1fhf_int_enR/W0b Enable Interrupt on False Carrier Counter Register half-full event
0rhf_int_enR/W0b Enable Interrupt on Receive Error Counter Register half-full event

8.6.2.8 MISR2 Register (Address = 13h) [Reset = 0000h]

MISR2 is shown in Figure 8-27 and described in Table 8-34.

Return to the Summary Table.

Figure 8-27 MISR2 Register
15141312111098
under_volt_intover_volt_intRESERVEDRESERVEDRESERVEDsleep_intpol_intjabber_int
H-0bH-0bH-0bH-0bH-0bH-0bH-0bH-0b
76543210
under_volt_int_enover_volt_int_enpage_rcvd_int_enFifo_int_enRESERVEDsleep_int_enpol_int_enjabber_int_en
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 8-34 MISR2 Register Field Descriptions
BitFieldTypeResetDescription
15under_volt_intH0b 1 = Under Voltage has been detected 0 =Under Voltage has not been detected
0b = Under Voltage has not been detected
1b = Under Voltage has been detected
14over_volt_intH0b 1 = Over Voltage has been detected 0 = Over Voltage has not been detected
0b = Over Voltage has not been detected
1b = Over Voltage has been detected
13RESERVEDH0b Reserved
12RESERVEDH0b Reserved
11RESERVEDH0b Reserved
10sleep_intH0b 1 = Sleep mode has changed 0 = Sleep mode has not changed
0b = Sleep mode has not changed
1b = Sleep mode has changed
9pol_intH0b The device has auto-polarity correction when operating in slave mode. This bit will reflect if polarity was automatically swapped or not.
0b = Data polarity has not changed
1b = Data polarity has changed
8jabber_intH0b 1 = Jabber detected 0 = Jabber not detected
0b = Jabber not detected
1b = Jabber detected
7under_volt_int_enR/W0b 0 = Disable interrupt
0b = Disable interrupt
6over_volt_int_enR/W0b 0 = Disable interrupt
0b = Disable interrupt
5page_rcvd_int_enR/W0b 1 = Enable interrupt
1b = Enable interrupt
4Fifo_int_enR/W0b 1 = Enable interrupt
1b = Enable interrupt
3RESERVEDR/W0b Reserved
2sleep_int_enR/W0b 1 = Enable interrupt
1b = Enable interrupt
1pol_int_enR/W0b 1 = Enable interrupt
1b = Enable interrupt
0jabber_int_enR/W0b 1 = Enable interrupt
1b = Enable interrupt

8.6.2.9 RECR Register (Address = 15h) [Reset = 0000h]

RECR is shown in Figure 8-28 and described in Table 8-35.

Return to the Summary Table.

Figure 8-28 RECR Register
15141312111098
rx_err_cnt
0b
76543210
rx_err_cnt
0b
Table 8-35 RECR Register Field Descriptions
BitFieldTypeResetDescription
15-0rx_err_cnt0b RX_ER Counter: When a valid carrier is presented (only while RX_DV is set), and there is at least one occurrence of an invalid data symbol, this 16-bit counter increments for each receive error detected. The RX_ER counter does not count in xMII loopback mode. The counter stops when it reaches its maximum count (0xFFFF). When the counter exceeds half-full (0x7FFF), an interrupt is generated. This register is cleared on read.

8.6.2.10 BISCR Register (Address = 16h) [Reset = 0100h]

BISCR is shown in Figure 8-29 and described in Table 8-36.

Return to the Summary Table.

Figure 8-29 BISCR Register
15141312111098
RESERVEDprbs_sync_lossRESERVEDcore_pwr_mode
R-0bH-0bR-0bR-1b
76543210
RESERVEDtx_mii_lpbkloopback_modepcs_lpbckRESERVED
R-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 8-36 BISCR Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR0b Reserved
10prbs_sync_lossH0b Prbs lock lost latch status
0b = Prbs lock never lost
1b = Prbs lock had been lost
9RESERVEDR0b Reserved
8core_pwr_modeR1b 1b0 = Core is in power down or sleep mode 1b1 = Core is is normal power mode
0b = Core is in power down or sleep mode
1b = Core is is normal power mode
7RESERVEDR0b Reserved
6tx_mii_lpbkR/W0b Transmit data control during xMII Loopback
0b = Suppress data during xMII loopback
1b = Transmit data on MDI during xMII loopback
5-2loopback_modeR/W0b Loopback Modes (Bit [1:0] must be 0)
1b = Digital Loopback
10b = Analog Loopback
100b = Reverse Loopback
1000b = External Loopback
1pcs_lpbckR/W0b PCS loopback after PAM3
0b = Disable PCS Loopback
1b = Enable PCS Loopback
0RESERVEDR/W0b Reserved

8.6.2.11 MISR3 Register (Address = 18h) [Reset = X]

MISR3 is shown in Figure 8-30 and described in Table 8-37.

Return to the Summary Table.

Figure 8-30 MISR3 Register
15141312111098
wup_psv_intno_link_intsleep_fail_intPOR_done_intno_frame_intwake_req_intWUP_sleep_intLPS_int
H-0bH-0bH-0bH-0bH-0bH-0bH-0bH-0b
76543210
wup_psv_int_enno_link_int_ensleep_fail_int_enPOR_done_int_enno_frame_int_enwake_req_int_enWUP_sleep_int_enLPS_int_en
R/W-XR/W-0bR/W-1bR/W-0bR/W-0bR/W-1bR/W-0bR/W-1b
Table 8-37 MISR3 Register Field Descriptions
BitFieldTypeResetDescription
15wup_psv_intH0b
0b = WUP are not received
1b = WUP received from remote PHY when in passive link
13sleep_fail_intH0b
0b = Sleep negotiation not failed yet
1b = Sleep negotiation failed
12POR_done_intH0b
0b = POR not completed yet
1b = POR completed (required for re-initialization of registers when we come out of sleep)
11no_frame_intH0b
0b = Frame was detected
1b = No Frame detected for transmission or reception in given time
10wake_req_intH0b
0b = Wake-up request not received
1b = Wake-up request command was received from remote PHY
9WUP_sleep_intH0b
0b = WUP not received
1b = WUP received from remote PHY when in sleep
8LPS_intH0b
0b = LPS symbols not detected
1b = LPS symbols detetced
7wup_psv_int_enR/WX
0b = Disable interrupt
1b = Enable interrupt
5sleep_fail_int_enR/W1b
0b = Disable interrupt
1b = Enable interrupt
4POR_done_int_enR/W0b
0b = Disable interrupt
1b = Enable interrupt
3no_frame_int_enR/W0b
0b = Disable interrupt
1b = Enable interrupt
2wake_req_int_enR/W1b
0b = Disable interrupt
1b = Enable interrupt
1WUP_sleep_int_enR/W0b
0b = Disable interrupt
1b = Enable interrupt
0LPS_int_enR/W1b
0b = Disable interrupt
1b = Enable interrupt

8.6.2.12 REG_19 Register (Address = 19h) [Reset = 0800h]

REG_19 is shown in Figure 8-31 and described in Table 8-38.

Return to the Summary Table.

Figure 8-31 REG_19 Register
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDdsp_energy_detectRESERVED
R-0bR-0bR-0bR-1bR-0bR-0b
76543210
RESERVEDPHY_ADDR
R-0bR-0b
Table 8-38 REG_19 Register Field Descriptions
BitFieldTypeResetDescription
15-14RESERVEDR0b Reserved
13RESERVEDR0b Reserved
12RESERVEDR0b Reserved
11RESERVEDR1b Reserved
10dsp_energy_detectR0b DSP energy detected status
9-5RESERVEDR0b Reserved
4-0PHY_ADDRR0b PHY address decode from straps

8.6.2.13 TC10_ABORT_REG Register (Address = 1Bh) [Reset = 0000h]

TC10_ABORT_REG is shown in Figure 8-32 and described in Table 8-39.

Return to the Summary Table.

Figure 8-32 TC10_ABORT_REG Register
15141312111098
RESERVED
R-0b
76543210
RESERVEDcfg_tc10_abort_gpio_encfg_sleep_abort
R-0bR/W-0bR/W-0b
Table 8-39 TC10_ABORT_REG Register Field Descriptions
BitFieldTypeResetDescription
15-2RESERVEDR0b Reserved
1cfg_tc10_abort_gpio_enR/W0b enables aborting TC10 via GPIO. one of CLKOUT/LED_1 pins which is being used as an LED can be used to abort
0b = disable TC10 abort via GPIO
1b = enable TC10 abort via GPIO
0cfg_sleep_abortR/W0b loc_sleep_abprt as defined by TC10 standard. Aborts sleep negotiation while in SLEEP_ACK state
0b = allow TC10 sleep negotiation
1b = abort TC10 sleep negotiation

8.6.2.14 CDCR Register (Address = 1Eh) [Reset = 0000h]

CDCR is shown in Figure 8-33 and described in Table 8-40.

Return to the Summary Table.

Figure 8-33 CDCR Register
15141312111098
tdr_start cfg_tdr_auto_runRESERVED
RH/W1S-0bR/W-0bR-0b
76543210
RESERVEDtdr_done tdr_fail
R-0bR-0bR-0b
Table 8-40 CDCR Register Field Descriptions
BitFieldTypeResetDescription
15tdr_start RH/W1S0b clr by tdr done Start TDR manually
0b = No TDR
1b = TDR start
14cfg_tdr_auto_runR/W0b Enable TDR auto run on link down
0b = TDR start manually
1b = TDR start automatically on link down
13-2RESERVEDR0b Reserved
1tdr_done R0b TDR done status
0b = TDR still not done
1b = TDR done
0tdr_failR0b TDR fail status

8.6.2.15 PHYRCR Register (Address = 1Fh) [Reset = 0000h]

PHYRCR is shown in Figure 8-34 and described in Table 8-41.

Return to the Summary Table.

Figure 8-34 PHYRCR Register
15141312111098
Software Global ResetDigital resetRESERVEDRESERVED
RH/W1S-0bRH/W1S-0bR/W-0bR/W-0b
76543210
Standby_modeRESERVEDRESERVEDRESERVED
R/W-0bR/W-0bR-0bR/W-0b
Table 8-41 PHYRCR Register Field Descriptions
BitFieldTypeResetDescription
15Software Global ResetRH/W1S0b Hardware Reset(Reset digital + register file)
0b = Normal Operation
1b = Reset PHY. This bit is self cleared and has the same effect as the RESET pin.
14Digital resetRH/W1S0b Software Restart
0b = Normal Operation
1b = Restart PHY. This bit is self cleared and resets all PHY circuitry except registers.
13RESERVEDR/W0b Reserved
12-8RESERVEDR/W0b Reserved
7Standby_modeR/W0b Standby Mode
0b = Normal operation
1b = Standby mode enabled
6RESERVEDR/W0b Reserved
5RESERVEDR0b Reserved
4-0RESERVEDR/W0b Reserved

8.6.2.16 Register_41 (Address = 41h) [Reset = 88F7h]

Register_41 is shown in Figure 8-35 and described in Table 8-42.

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Figure 8-35 Register_41
15141312111098
cfg_ether_type_pattern
R/W-1000100011110111b
76543210
cfg_ether_type_pattern
R/W-1000100011110111b
Table 8-42 Register_41 Field Descriptions
BitFieldTypeResetDescription
15-0cfg_ether_type_patternR/W1000100011110111b Ethertype pattern to be detected when 0x40[0] is enabled

8.6.2.17 Register_133 (Address = 133h) [Reset = 0000h]

Register_133 is shown in Figure 8-36 and described in Table 8-43.

Return to the Summary Table.

Figure 8-36 Register_133
15141312111098
RESERVEDlink_up_c_and_slink_status_pclink_statusRESERVED
R-0bR-0bR-0bR-0bR-0b
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDdescr_syncloc_rcvr_statusrem_rcvr_status
R-0bR-0bR-0bR-0bR-0bR-0bR-0bR-0b
Table 8-43 Register_133 Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0b Reserved
11-8RESERVEDR0b Reserved
7RESERVEDR0b Reserved
6RESERVEDR0b Reserved
5RESERVEDR0b Reserved
4RESERVEDR0b Reserved
3RESERVEDR0b Reserved
2descr_syncR0b Status of descrambler
0b = Scrambler Not Locked
1b = Scrambler Locked
1loc_rcvr_statusR0b Local receiver status
0b = Local PHY received link invalid
1b = Local PHY received link valid
0rem_rcvr_statusR0b Remote receiver status
0b = Remote PHY received link invalid
1b = Remote PHY received link valid

8.6.2.18 Register_17F (Address = 17Fh) [Reset = 4028h]

Register_17F is shown in Figure 8-37 and described in Table 8-44.

Return to the Summary Table.

Figure 8-37 Register_17F
15141312111098
cfg_en_wur_via_wakecfg_en_wup_via_wakeRESERVED
R/W-0bR/W-1bR-0b
76543210
cfg_wake_pin_len_fr_wur_th
R/W-101000b
Table 8-44 Register_17F Field Descriptions
BitFieldTypeResetDescription
15cfg_en_wur_via_wakeR/W0b enable sending WUR when wake pin is asserted during active link. Duration of pulse on WAKE pin can be configured in 0x17F[7:0]
0b = disable sending WUR when pulse on wake pin
1b = enable sending WUR when pulse on wake pin
14cfg_en_wup_via_wakeR/W1b enable sending WUP when device is woken by WAKE pin
0b = disables WUP
1b = enables WUP
13-8RESERVEDR0b Reserved
7-0cfg_wake_pin_len_fr_wur_thR/W101000b Width of pulse in microseconds required to initiate WUR during an active link

8.6.2.19 Register_180 (Address = 180h) [Reset = 0000h]

Register_180 is shown in Figure 8-38 and described in Table 8-45.

Return to the Summary Table.

Figure 8-38 Register_180
15141312111098
RESERVED
R-0b
76543210
RESERVEDcfg_sleep_req_timer_selRESERVEDcfg_sleep_ack_timer_sel
R-0bR/W-0bR-0bR/W-0b
Table 8-45 Register_180 Field Descriptions
BitFieldTypeResetDescription
15-5RESERVEDR0b Reserved
4-3cfg_sleep_req_timer_selR/W0b Configure sleep request timer
0b = 16ms
1b = 4ms
10b = 32ms
11b = 40ms
2RESERVEDR0b Reserved
1-0cfg_sleep_ack_timer_selR/W0b Configure sleep acknowledge timer
0b = 8ms
1b = 6ms
10b = 24ms
11b = 32ms

8.6.2.20 Register_181 (Address = 181h) [Reset = 0000h]

Register_181 is shown in Figure 8-39 and described in Table 8-46.

Return to the Summary Table.

Figure 8-39 Register_181
15141312111098
RESERVEDrx_lps_cnt
R-0bR-0b
76543210
rx_lps_cnt
R-0b
Table 8-46 Register_181 Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0b Reserved
9-0rx_lps_cntR0b indicates number of LPS codes received

8.6.2.21 Register_182 (Address = 182h) [Reset = 0000h]

Register_182 is shown in Figure 8-40 and described in Table 8-47.

Return to the Summary Table.

Figure 8-40 Register_182
15141312111098
RESERVEDtx_lps_cnt
R-0bR-0b
76543210
tx_lps_cnt
R-0b
Table 8-47 Register_182 Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0b Reserved
9-0tx_lps_cntR0b indicates number of WUR codes received

8.6.2.22 LPS_CFG4 Register (Address = 183h) [Reset = 0000h]

LPS_CFG4 is shown in Figure 8-41 and described in Table 8-48.

Return to the Summary Table.

Figure 8-41 LPS_CFG4 Register
15141312111098
cfg_send_wup_dis_tx cfg_force_lps_sleep_encfg_force_lps_sleepcfg_force_tx_lps_encfg_force_tx_lpscfg_force_lps_link_control_encfg_force_lps_link_controlcfg_force_lps_st_en
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
76543210
RESERVEDcfg_force_lps_st
R-0bR/W-0b
Table 8-48 LPS_CFG4 Register Field Descriptions
BitFieldTypeResetDescription
15cfg_send_wup_dis_tx R/W0b Write 1 to this bit to send WUP when PHY control is in DISABLE_TRANSMIT state
14cfg_force_lps_sleep_enR/W0b force control enable for sleep from LPS SM to PHY control SM
13cfg_force_lps_sleepR/W0b force value for sleep from LPS SM to PHY control SM
12cfg_force_tx_lps_enR/W0b force enable for TX_LPS
11cfg_force_tx_lpsR/W0b force value for TX_LPS
8cfg_force_lps_st_enR/W0b force enable for LPS state machine
7RESERVEDR0b Reserved
6-0cfg_force_lps_stR/W0b force value of LPS state machine

8.6.2.23 LPS_CFG Register (Address = 184h) [Reset = 0223h]

LPS_CFG is shown in Figure 8-42 and described in Table 8-49.

Return to the Summary Table.

Figure 8-42 LPS_CFG Register
15141312111098
cfg_reset_wur_cnt_rx_dataRESERVEDcfg_reset_lps_cnt_rx_dataRESERVEDcfg_reset_wur_cnt_tx_dataRESERVED
R/W-0bR-0bR/W-0bR-0bR/W-1bR-0b
76543210
RESERVEDcfg_reset_lps_cnt_tx_datacfg_wake_fwd_en_wup_psv_linkcfg_wake_fwd_man_trigcfg_wake_fwd_dig_timercfg_wake_fwd_en_wurcfg_wake_fwd_en_wup
R-0bR/W-0bR/W-1bR/W-0bR/W-0bR/W-1bR/W-1b
Table 8-49 LPS_CFG Register Field Descriptions
BitFieldTypeResetDescription
15cfg_reset_wur_cnt_rx_dataR/W0b When set, resets the WUR received symbol counter upon receiving data
14-13RESERVEDR0b Reserved
12cfg_reset_lps_cnt_rx_dataR/W0b When set, resets the LPS received symbol counter upon receiving data
11-10RESERVEDR0b Reserved
9cfg_reset_wur_cnt_tx_dataR/W1b When set, resets the transmitted WUR symbols count when sending data
8-7RESERVEDR0b Reserved
6cfg_reset_lps_cnt_tx_dataR/W0b When set, resets the transmitted LPS symbols count when sending data
4cfg_wake_fwd_man_trigR/W0b Write 1 to manually generate Wake forwarding signal on WAKE pin. This bit is self-cleared
3-2cfg_wake_fwd_dig_timerR/W0b when wake up request is received on an active link, the width of wake forwarding pulses are configurable to : 00: 50us 01: 500us 10: 2ms 11: 20ms
1cfg_wake_fwd_en_wurR/W1b If set, enables doing wake forwarding when WUR symbols are received
0b = Don 't do wake forwarding on WAKE pin
1b = do wake forwarding on WAKE pin
0cfg_wake_fwd_en_wupR/W1b If set, enables doing wake forwarding when WUP symbols are received
0b = Don 't do wake forwarding on WAKE pin
1b = do wake forwarding on WAKE pin

8.6.2.24 LPS_CFG5 Register (Address = 185h) [Reset = 0000h]

LPS_CFG5 is shown in Figure 8-43 and described in Table 8-50.

Return to the Summary Table.

Figure 8-43 LPS_CFG5 Register
15141312111098
cfg_wup_timerRESERVED
R/W-0bR-0b
76543210
RESERVEDcfg_rx_wur_sym_gapcfg_rx_lps_sym_gap
R-0bR/W-0bR/W-0b
Table 8-50 LPS_CFG5 Register Field Descriptions
BitFieldTypeResetDescription
15-13cfg_wup_timerR/W0b Time for which PHY control SM stays in WAKE_TRANSMIT b000: 1ms b001: 0.7ms b010: 1.3ms b011: 0.85ms b100: 1.5ms b101: 2ms b110: 2.5ms b111: 3ms
12-4RESERVEDR0b Reserved
3-2cfg_rx_wur_sym_gapR/W0b max gap allowed b/w two WUR symbols for ack of WUR
1-0cfg_rx_lps_sym_gapR/W0b max gap allowed b/w two LPS symbols for ack of LPS

8.6.2.25 LPS_CFG7 Register (Address = 187h) [Reset = 0000h]

LPS_CFG7 is shown in Figure 8-44 and described in Table 8-51.

Return to the Summary Table.

Figure 8-44 LPS_CFG7 Register
15141312111098
cfg_tx_lps_stop_on_doneRESERVED
R/W-0bR-0b
76543210
cfg_tx_lps_sel
R/W-0b
Table 8-51 LPS_CFG7 Register Field Descriptions
BitFieldTypeResetDescription
15cfg_tx_lps_stop_on_doneR/W0b configures the device to stop sending LPS codes once it is done sending the number of codes configures in 0x1879:0
0b = continues even after reaching limit
1b = stops after reaching limit
14-8RESERVEDR0b Reserved
9-0cfg_tx_lps_selR/W0b Indicates number of LPS symbols to be transmitted before tx_lps_done becomes true

8.6.2.26 LPS_CFG8 Register (Address = 188h) [Reset = 0080h]

LPS_CFG8 is shown in Figure 8-45 and described in Table 8-52.

Return to the Summary Table.

Figure 8-45 LPS_CFG8 Register
15141312111098
RESERVEDcfg_tx_wur_sel
R-0bR/W-10000000b
76543210
cfg_tx_wur_sel
R/W-10000000b
Table 8-52 LPS_CFG8 Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0b Reserved
9-0cfg_tx_wur_selR/W10000000b Indicates number of WUR symbols to be transmitted

8.6.2.27 LPS_CFG9 Register (Address = 189h) [Reset = 0040h]

LPS_CFG9 is shown in Figure 8-46 and described in Table 8-53.

Return to the Summary Table.

Figure 8-46 LPS_CFG9 Register
15141312111098
RESERVEDcfg_rx_lps_sel
R-0bR/W-1000000b
76543210
cfg_rx_lps_sel
R/W-1000000b
Table 8-53 LPS_CFG9 Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0b Reserved
9-0cfg_rx_lps_selR/W1000000b Indicates number of LPS symbols to be received to set lps_recv

8.6.2.28 LPS_CFG10 Register (Address = 18Ah) [Reset = 0040h]

LPS_CFG10 is shown in Figure 8-47 and described in Table 8-54.

Return to the Summary Table.

Figure 8-47 LPS_CFG10 Register
15141312111098
RESERVEDcfg_rx_wur_sel
R-0bR/W-1000000b
76543210
cfg_rx_wur_sel
R/W-1000000b
Table 8-54 LPS_CFG10 Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0b Reserved
9-0cfg_rx_wur_selR/W1000000b Indicates number of WUR symbols to be received to acknowlege WUR and do wake forwarding

8.6.2.29 LPS_CFG3 Register (Address = 18Ch) [Reset = 0000h]

LPS_CFG3 is shown in Figure 8-48 and described in Table 8-55.

Return to the Summary Table.

Figure 8-48 LPS_CFG3 Register
15141312111098
RESERVEDcfg_lps_pwr_mode
R-0bRH/W1S-0b
76543210
cfg_lps_pwr_mode
RH/W1S-0b
Table 8-55 LPS_CFG3 Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR0b Reserved
8-0cfg_lps_pwr_modeRH/W1S0b
1b = Normal command
10b = Sleep request
10000b = Standby command
10000000b = WUR command
100000000b = Go to Passive Link command

8.6.2.30 LPS_STATUS Register (Address = 18Eh) [Reset = 0000h]

LPS_STATUS is shown in Figure 8-49 and described in Table 8-56.

Return to the Summary Table.

Figure 8-49 LPS_STATUS Register
15141312111098
RESERVED
R-0b
76543210
RESERVEDstatus_lps_st
R-0bR-0b
Table 8-56 LPS_STATUS Register Field Descriptions
BitFieldTypeResetDescription
15-7RESERVEDR0b Reserved
6-0status_lps_stR0b LPS SM state
1b = SLEEP
10b = STANDBY
100b = NORMAL
1000b = SLEEP_ACK
10000b = SLEEP_REQ
100000b = SLEEP_FAIL
1000000b = SLEEP_SILENT
1000001b = PASSIVE_LINK

8.6.2.31 TDR_TX_CFG Register (Address = 300h) [Reset = 2710h]

TDR_TX_CFG is shown in Figure 8-50 and described in Table 8-57.

Return to the Summary Table.

Figure 8-50 TDR_TX_CFG Register
15141312111098
cfg_tdr_tx_duration
R/W-10011100010000b
76543210
cfg_tdr_tx_duration
R/W-10011100010000b
Table 8-57 TDR_TX_CFG Register Field Descriptions
BitFieldTypeResetDescription
15-0cfg_tdr_tx_durationR/W10011100010000b TDR transmit duration in usec, Default : 10000usec

8.6.2.32 TAP_PROCESS_CFG Register (Address = 301h) [Reset = 1703h]

TAP_PROCESS_CFG is shown in Figure 8-51 and described in Table 8-58.

Return to the Summary Table.

Figure 8-51 TAP_PROCESS_CFG Register
15141312111098
RESERVEDcfg_end_tap_index
R-0bR/W-10111b
76543210
RESERVEDcfg_start_tap_index
R-0bR/W-11b
Table 8-58 TAP_PROCESS_CFG Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR0b Reserved
12-8cfg_end_tap_indexR/W10111b End echo coefficient index for peak detect sweep during TDR
7-5RESERVEDR0b Reserved
4-0cfg_start_tap_indexR/W11b Starting echo coefficient index for peak detect sweep during TDR

8.6.2.33 TDR_CFG1 Register (Address = 302h) [Reset = 0045h]

TDR_CFG1 is shown in Figure 8-52 and described in Table 8-59.

Return to the Summary Table.

Figure 8-52 TDR_CFG1 Register
15141312111098
RESERVED
R-0b
76543210
cfg_forward_shadowcfg_post_silence_timecfg_pre_silence_time
R/W-100bR/W-1bR/W-1b
Table 8-59 TDR_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR0b Reserved
7-4cfg_forward_shadowR/W100b Num of neighboring echo coeff taps to be considered for calculating local maximum
3-2cfg_post_silence_timeR/W1b Post-Silence state timer in ms 0x00 : 0ms 0x01 : 10ms 0x10 : 100ms 0x11 : 1000ms
1-0cfg_pre_silence_timeR/W1b Pre-Silence state timer in ms 0x00 : 0ms 0x01 : 10ms 0x10 : 100ms 0x11 : 1000ms

8.6.2.34 TDR_CFG2 Register (Address = 303h) [Reset = 0419h]

TDR_CFG2 is shown in Figure 8-53 and described in Table 8-60.

Return to the Summary Table.

Figure 8-53 TDR_CFG2 Register
15141312111098
RESERVEDcfg_tdr_filt_loc_offset
R-0bR/W-100b
76543210
cfg_tdr_filt_init
R/W-11001b
Table 8-60 TDR_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR0b Reserved
12-8cfg_tdr_filt_loc_offsetR/W100b tap index offset of dyamic peak equation, cfg_start_tap_index + 1'b1
7-0cfg_tdr_filt_initR/W11001b Value of peak_th at x=start_tap_index of dynamic peak threshold equation

8.6.2.35 TDR_CFG3 Register (Address = 304h) [Reset = 0030h]

TDR_CFG3 is shown in Figure 8-54 and described in Table 8-61.

Return to the Summary Table.

Figure 8-54 TDR_CFG3 Register
15141312111098
RESERVED
R-0b
76543210
cfg_tdr_filt_slope
R/W-110000b
Table 8-61 TDR_CFG3 Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR0b Reserved
7-0cfg_tdr_filt_slopeR/W110000b Slope of dynamic peak threshold equation (0.4)

8.6.2.36 TDR_CFG4 Register (Address = 305h) [Reset = 0004h]

TDR_CFG4 is shown in Figure 8-55 and described in Table 8-62.

Return to the Summary Table.

Figure 8-55 TDR_CFG4 Register
15141312111098
RESERVEDRESERVEDRESERVED
R-0bR/W-0bR/W-0b
76543210
RESERVEDRESERVEDhpf_gain_tdrpga_gain_tdr
R/W-0bR/W-0bR/W-0bR/W-100b
Table 8-62 TDR_CFG4 Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0b Reserved
9RESERVEDR/W0b Reserved
8-7RESERVEDR/W0b Reserved
6RESERVEDR/W0b Reserved
5-4hpf_gain_tdrR/W0b HPF gain code during TDR
3-0pga_gain_tdrR/W100b PGA gain code during TDR

8.6.2.37 TDR_CFG5 Register (Address = 306h) [Reset = 000Ah]

TDR_CFG5 is shown in Figure 8-56 and described in Table 8-63.

Return to the Summary Table.

Figure 8-56 TDR_CFG5 Register
15141312111098
RESERVED
R-0b
76543210
RESERVEDcfg_half_open_det_encfg_cable_delay_num
R-0bR/W-0bR/W-1010b
Table 8-63 TDR_CFG5 Register Field Descriptions
BitFieldTypeResetDescription
15-5RESERVEDR0b Reserved
4cfg_half_open_det_enR/W0b enables detection of half cable
0b = Disables half open detection
1b = Enbales half open detection
3-0cfg_cable_delay_numR/W1010b Configure the propagation delay per meter of the cable in nanoseconds. This is used for the fault location estimation Valid values : 4 'd0 to 4 'd11 - [4.5:0.1:5.6]ns Default : 4 'd10 (5.5 ns)

8.6.2.38 TDR_TC1 Register (Address = 310h) [Reset = 0000h]

TDR_TC1 is shown in Figure 8-57 and described in Table 8-64.

Return to the Summary Table.

Figure 8-57 TDR_TC1 Register
15141312111098
RESERVEDhalf_open_detect
R-0bR-0b
76543210
peak_detectpeak_signpeak_loc_in_meters
R-0bR-0bR-0b
Table 8-64 TDR_TC1 Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR0b Reserved
8half_open_detectR0b Half wire open detect value
0b = Half wire open not detected
1b = Half wire open detected
7peak_detectR0b Set if fault is detected in cable
0b = Fault not detected in cable
1b = Fault detected in cable
6peak_signR0b Nature of discontinuity. Valid only if peak_detect is set
0b = Short to GND, supply, or between MDI pins
1b = Open. Applicable to both 1-wire and 2-wire open faults
5-0peak_loc_in_metersR0b Fault location in meters (Valid only if peak_detect is set)

8.6.2.39 A2D_REG_48 Register (Address = 430h) [Reset = 0770h]

A2D_REG_48 is shown in Figure 8-58 and described in Table 8-65.

Return to the Summary Table.

Figure 8-58 A2D_REG_48 Register
15141312111098
RESERVEDRESERVEDdll_tx_delay_ctrl_rgmii_sl
R-0bR/W-0bR/W-111b
76543210
dll_rx_delay_ctrl_rgmii_slRESERVED
R/W-111bR/W-0b
Table 8-65 A2D_REG_48 Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR0b Reserved
12RESERVEDR/W0b Reserved
11-8dll_tx_delay_ctrl_rgmii_slR/W111b controls TX DLL in RGMII mode inSteps of 312.5ps, affects the CLK_90 output.
Delay = ((Bit[11:8] in decimal) + 1)*312.5 ps
7-4dll_rx_delay_ctrl_rgmii_slR/W111b Controls RX DLL in RGMII mode in Steps of 312.5ps, affects the CLK_90 output.
Delay = ((Bit[7:4] in decimal) + 1)*312.5 ps
3-0RESERVEDR/W0b Reserved

8.6.2.40 LEDS_CFG_1 Register (Address = 450h) [Reset = 2610h]

LEDS_CFG_1 is shown in Figure 8-59 and described in Table 8-66.

Return to the Summary Table.

Figure 8-59 LEDS_CFG_1 Register
15141312111098
RESERVEDleds_bypass_stretchingleds_blink_rateled_2_option
R-0bR/W-0bR/W-10bR/W-110b
76543210
led_1_optionled_0_option
R/W-1bR/W-0b
Table 8-66 LEDS_CFG_1 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0b Reserved
14leds_bypass_stretchingR/W0b 0 - Noraml Operation 1 - Bypass LEDs stretching
0b = Noraml Operation
1b = Bypass LEDs stretching
11-8led_2_optionR/W110b Controlls LED_2 sources
(same as bits 3:0)
7-4led_1_optionR/W1b Controlls LED_1 sources
(same as bits 3:0)
3-0led_0_optionR/W0b Controlls LED_0 source:
0b = link OK
1b = link OK + blink on TX/RX activity
10b = link OK + blink on TX activity
11b = link OK + blink on RX activity
100b = link OK + 100Base-T1 Master
101b = link OK + 100Base-T1 Slave
110b = TX/RX activity with stretch option
111b = Reserved
1000b = Reserved
1001b = Link lost (remains on until register 0x1 is read)
1010b = PRBS error (toggles on error)
1011b = XMII TX/RX Error with stretch option

8.6.2.41 LEDS_CFG_2 Register (Address = 451h) [Reset = 0049h]

LEDS_CFG_2 is shown in Figure 8-60 and described in Table 8-67.

Return to the Summary Table.

Figure 8-60 LEDS_CFG_2 Register
15141312111098
clk_o_gpio_ctrl_3led_1_gpio_ctrl_3led_0_gpio_ctrl_3RESERVEDled_2_drv_en
R/W-0bR/W-0bR/W-0bR-0bR/W-0b
76543210
led_2_drv_valled_2_polarityled_1_drv_enled_1_drv_valled_1_polarityled_0_drv_enled_0_drv_valled_0_polarity
R/W-0bR/W-1bR/W-0bR/W-0bR/W-1bR/W-0bR/W-0bR/W-1b
Table 8-67 LEDS_CFG_2 Register Field Descriptions
BitFieldTypeResetDescription
15clk_o_gpio_ctrl_3R/W0b MSB of CLKOUT gpio control. This bit provides additional options for configuring CLKOUT
If set to 1, it changes the effect ofclk_o_gpio_ctrl bits of 0x453
Reg 0x453[2:0] will control CLKOUT as follows

0b = pwr_seq_done
1b = loc_wake_req from analog
10b = loc_wake_req to PHY control
11b = tx_lps_done
100b = tx_lps_done_64
101b = tx_lps
110b = pcs rx sm - receiving
111b = pcs tx sm - tx_enable
14led_1_gpio_ctrl_3R/W0b MSB of LED_1 gpio control. This bit provides additional options for configuring LED_0
If set to 1, it changes the effect of led_1_gpio_ctrl bits of 0x452
Reg 0x452[10:8] will control LED_1 as follows

0b = pwr_seq_done
1b = loc_wake_req from analog
10b = loc_wake_req to PHY control
11b = tx_lps_done
100b = tx_lps_done_64
101b = tx_lps
110b = pcs rx sm - receiving
111b = pcs tx sm - tx_enable
13led_0_gpio_ctrl_3R/W0b MSB of LED_0 gpio control. This bit provides additional options for configuring LED_0
If set to 1, it changes the effect of led_0_gpio_ctrl bits of 0x452
Reg 0x452[2:0] will control LED_0 as follows

0b = pwr_seq_done
1b = loc_wake_req from analog
10b = loc_wake_req to PHY control
11b = tx_lps_done
100b = tx_lps_done_64
101b = tx_lps
110b = pcs rx sm - receiving
111b = pcs tx sm - tx_enable
12-9RESERVEDR0b Reserved
8led_2_drv_enR/W0b 0 - LED_2 is in normal operation mode 1 - Drive the value of LED_2 (driven value is bit 9)
0b = LED_2 is in normal operation mode
1b = Drive the value of LED_2 (driven value is bit 9)
7led_2_drv_valR/W0b If bit #8 is set, this is the value of LED_2
6led_2_polarityR/W1b LED_2 polarity
0b = Active low
1b = Active high
5led_1_drv_enR/W0b 0 - LED_1 is in normal operation mode 1 - Drive the value of LED_1 (driven value is bit #5)
0b = LED_1 is in normal operation mode
1b = Drive the value of LED_1 (driven value is bit #5)
4led_1_drv_valR/W0b If bit #4 is set, this is the value of LED_1
3led_1_polarityR/W1b LED_1 polarity: if(RX_D3_strap == 1) reset_val = ~CLKOUT_strap else reset_val = ~LED_1_strap
0b = Active low
1b = Active high
2led_0_drv_enR/W0b 0 - LED_0 is in normal operation mode 1 - Drive the value of LED_0 (driven value is bit #1)
1led_0_drv_valR/W0b If bit #1 is set, this is the value of LED_1
0led_0_polarityR/W1b LED_0 polarity: reset_val = ~LED_0_strap
0b = Active low
1b = Active high

8.6.2.42 IO_MUX_CFG_1 Register (Address = 452h) [Reset = 0000h]

IO_MUX_CFG_1 is shown in Figure 8-61 and described in Table 8-68.

Return to the Summary Table.

Figure 8-61 IO_MUX_CFG_1 Register
15141312111098
led_1_clk_div_2_enled_1_clk_sourceled_1_clk_inv_enled_1_gpio_ctrl
R/W-0bR/W-0bR/W-0bR/W-0b
76543210
led_0_clk_div_2_enled_0_clk_sourceled_0_clk_inv_enled_0_gpio_ctrl
R/W-0bR/W-0bR/W-0bR/W-0b
Table 8-68 IO_MUX_CFG_1 Register Field Descriptions
BitFieldTypeResetDescription
15led_1_clk_div_2_enR/W0b If led_1_gpio is configured to led_1_clk_source, Selects divide by 2 of clock at led_1_clk_source
14-12led_1_clk_sourceR/W0b In case clk_out is MUXed to LED_1 IO, this field controls clk_out source:
000b - XI clock
001b - 200M pll clock
010b - 67 MHz ADC clock (recovered)
011b - Free 200MHz clock
100b - 25M MII clock derived from 200M LD clock
101b - 25MHz clock to PLL (XI or XI/2) or POR clock
110b - Core 100 MHz clock
111b - 67 MHz DSP clock (recovered, 1/3 duty cycle)
11led_1_clk_inv_enR/W0b If led_1_gpio is configured to led_1_clk_source, Selects inversion of clock at led_1_clk_source
10-8led_1_gpio_ctrlR/W0b controls the output of LED_1 IO:
000b - LED_1 (default: LINK + ACT)
001b - LED_1 Clock mux out
010b - WoL
011b - Under-Voltage indication
100b - 1588 TX
101b - 1588 RX
110b - ESD
111b - interrupt

if(RX_D3_strap ==1)
reset_val = 3'b001
else
reset_val = 3'b000
7led_0_clk_div_2_enR/W0b If led_0_gpio is configured to led_0_clk_source, Selects divide by 2 of clock at led_0_clk_source
6-4led_0_clk_sourceR/W0b In case clk_out is MUXed to LED_0 IO, this field controls clk_out source:
0b = XI clock
1b = 200M pll clock
10b = 67 MHz ADC clock (recovered)
11b = Free 200MHz clock
100b = 25M MII clock derived from 200M LD clock
101b = 25MHz clock to PLL (XI or XI/2) or POR clock
110b = Core 100 MHz clock
111b = 67 MHz DSP clock (recovered, 1/3 duty cycle)
3led_0_clk_inv_enR/W0b If led_0_gpio is configured to led_0_clk_source, Selects inversion of clock at led_0_clk_source
2-0led_0_gpio_ctrlR/W0b controls the output of LED_0 IO:
0b = LED_0 (default: LINK) 001b =LED_0 Clock mux out 010b = WoL 011b = Under-Voltage indication 100b = 1588 TX 101b = 1588 RX 110b = ESD 111b = interrupt

8.6.2.43 IO_MUX_CFG_2 Register (Address = 453h) [Reset = 0001h]

IO_MUX_CFG_2 is shown in Figure 8-62 and described in Table 8-69.

Return to the Summary Table.

Figure 8-62 IO_MUX_CFG_2 Register
15141312111098
cfg_tx_er_on_led1RESERVEDclk_o_clk_div_2_en
R/W-0bR-0bR/W-0b
76543210
clk_o_clk_sourceclk_o_clk_inv_enclk_o_gpio_ctrl
R/W-0bR/W-0bR/W-1b
Table 8-69 IO_MUX_CFG_2 Register Field Descriptions
BitFieldTypeResetDescription
15cfg_tx_er_on_led1R/W0b configures led_1 pin to tx_er pin and LED_1 pin is made input
14-9RESERVEDR0b Reserved
8clk_o_clk_div_2_enR/W0b If clk_out is configured to output clk_o_clk_source, Selects divide by 2 of clock at clk_o_clk_source
7-4clk_o_clk_sourceR/W0b In case clk_out is MUXed to CLK_O IO, this field controls clk_out source: 0000b - XI clock
0001b - 200M pll clock
0010b - 67 MHz ADC clock (recovered)
0011b - Free 200MHz clock
0100b - 25M MII clock derived from 200M LD clock
0101b - 25MHz clock to PLL (XI or XI/2) or POR clock
0110b - Core 100 MHz clock
0111b - 67 MHz DSP clock (recovered, 1/3 duty cycle)
1000b - CLK25_50 (50 MHz in RMII, 25 MHz in others)
1001b - 50M RMII RX clk
1010b - SGMII serlz clk
1011b - SGMII deserlz clk
1100b - 30ns tick
1101b - 40ns tick
1110b - DLL TX CLK
1111b - DLL RX CLK
3clk_o_clk_inv_enR/W0b If clk_out is configured to output clk_o_clk_source, Selects inversion of clock at clk_o_clk_source
2-0clk_o_gpio_ctrlR/W1b controls the output of CLK_O IO:
000b - LED_1
001b - CLKOUT Clock mux out
010b - WoL
011b - Under-Voltage indication
100b - 1588 TX
101b - 1588 RX
110b - ESD
111b - interrupt
Automatically gets configured
to 3 'h0 if pin6(LED_1) is strapped
As daisy chain CLKOUT

if(RX_D3_strap ==1)
reset_val = 3'b000
else
reset_val = 3'b001

8.6.2.44 IO_MUX_CFG Register (Address = 456h) [Reset = 0000h]

IO_MUX_CFG is shown in Figure 8-63 and described in Table 8-70.

Return to the Summary Table.

Figure 8-63 IO_MUX_CFG Register
15141312111098
rx_pins_pupd_valuerx_pins_pupd_force_controltx_pins_pupd_valuetx_pins_pupd_force_controlmac_rx_impedance_ctrl
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
76543210
mac_rx_impedance_ctrlmac_tx_impedance_ctrl
R/W-0bR/W-0b
Table 8-70 IO_MUX_CFG Register Field Descriptions
BitFieldTypeResetDescription
15-14rx_pins_pupd_valueR/W0b when RX pins PUPD force control is enabled, PUPD is contolled by this register
0b = No pull
1b = Pull up
10b = Pull down
11b = Reserved
13rx_pins_pupd_force_controlR/W0b enables PUPD force control on RX MAC pins
0b = No force control
1b = enables force control
12-11tx_pins_pupd_valueR/W0b when TX pins PUPD force control is enabled, PUPD is contolled by this register
0b = No pull
1b = Pull up
10b = Pull down
11b = Reserved
10tx_pins_pupd_force_controlR/W0b enables PUPD force control on TX MAC pins
0b = No force control
1b = enables force control
9-5mac_rx_impedance_ctrlR/W0b RX MAC interface PAD impedance control
4-0mac_tx_impedance_ctrlR/W0b TX MAC interface PAD impedance control

8.6.2.45 IO_STATUS_1 Register (Address = 457h) [Reset = 0000h]

IO_STATUS_1 is shown in Figure 8-64 and described in Table 8-71.

Return to the Summary Table.

Figure 8-64 IO_STATUS_1 Register
15141312111098
io_status_1
R-0b
76543210
io_status_1
R-0b
Table 8-71 IO_STATUS_1 Register Field Descriptions
BitFieldTypeResetDescription
15-0io_status_1R0b If IO direction is controlled via register (IO_MUX_CFG) and (IO_INPUT_MODE_1), and direction is INPUT
(i.e. io_oe_n_force_ctrl=1, io_input_mode[*]=1) - shows the current value of the following IOs:
bit 0 - RX_D3
bit 1 - TX_CLK
bit 2 - TX_EN
bit 3 - TX_D0
bit 4 - TX_D1
bit 5 - TX_D2
bit 6 - TX_D3
bit 7 - INT_N
bit 8 - CLKOUT
bit 9 - LED_0
bit 10 - RX_CLK
bit 11 - RX_DV
bit 12 - 0
bit 13 - RX_ERR
bit 14 - LED_1
bit 15 - RX_D0

8.6.2.46 IO_STATUS_2 Register (Address = 458h) [Reset = 0000h]

IO_STATUS_2 is shown in Figure 8-65 and described in Table 8-72.

Return to the Summary Table.

Figure 8-65 IO_STATUS_2 Register
15141312111098
RESERVED
R-0b
76543210
RESERVEDio_status_2
R-0bR-0b
Table 8-72 IO_STATUS_2 Register Field Descriptions
BitFieldTypeResetDescription
15-2RESERVEDR0b Reserved
1-0io_status_2R0b "If IO direction is controlled via register (IO_MUX_CFG) and (IO_INPUT_MODE_2), and direction is INPUT (i.e. io_oe_n_force_ctrl=1, io_input_mode[*]=1) - shows the current value of the following IOs: bit 0 - RX_D1 bit 1 - RX_D2 "

8.6.2.47 CHIP_SOR_1 Register (Address = 45Dh) [Reset = 0000h]

CHIP_SOR_1 is shown in Figure 8-66 and described in Table 8-73.

Return to the Summary Table.

Figure 8-66 CHIP_SOR_1 Register
15141312111098
RESERVEDRESERVEDLED1_PORRX_D3_PORRESERVEDRESERVEDLED0_STRAPRXD3_STRAP
R-0bR-0bR-0bR-0bR-0bR-0bR-0bR-0b
76543210
RXD2_STRAPRXD1_STRAPRXD0_STRAPRXCLK_STRAPRXER_STRAPRXDV_STRAP
R-0bR-0bR-0bR-0bR-0bR-0b
Table 8-73 CHIP_SOR_1 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0b
14RESERVEDR0b Reserved
13LED1_PORR0b LED_1 strap sampled at power up
12RX_D3_PORR0b RX_D3 strap sampled at power up
11RESERVEDR0b Reserved
10RESERVEDR0b Reserved
9LED0_STRAPR0b LED_0 strap sampled at power up or reset
8RXD3_STRAPR0b RX_D3 strap sampled at reset
7RXD2_STRAPR0b RX_D2 strap sampled at power up or reset
6RXD1_STRAPR0b RX_D1 strap sampled at power up or reset
5RXD0_STRAPR0b RX_D0 strap sampled at power up or reset
4RXCLK_STRAPR0b RX_CLK strap sampled at power up or reset
3-2RXER_STRAPR0b RX_ER strap sampled at power up or reset
1-0RXDV_STRAPR0b RX_DV strap sampled at power up or reset

8.6.2.48 LED1_CLKOUT_ANA_CTRL Register (Address = 45Fh) [Reset = 000Ch]

LED1_CLKOUT_ANA_CTRL is shown in Figure 8-67 and described in Table 8-74.

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Figure 8-67 LED1_CLKOUT_ANA_CTRL Register
15141312111098
RESERVEDRESERVEDRESERVED
R/W-0bR/W-0bR-0b
76543210
RESERVEDclkout_ana_sel_1p0v_slled_1_ana_mux_ctrlclkout_ana_mux_ctrl
R-0bR/W-0bR/W-11bR/W-0b
Table 8-74 LED1_CLKOUT_ANA_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0b Reserved
14RESERVEDR/W0b Reserved
13-5RESERVEDR0b Reserved
4clkout_ana_sel_1p0v_slR/W0b For selecting test line b/w analog test clocks
3-2led_1_ana_mux_ctrlR/W11b Selects the signal to be sent out on LED_1 pin Automatically selects output from digital if Pin6(LED_1) is strapped As daisy chain CLKOUT if(RX_D3_strap == 1) reset_val = 2'b00 else reset_val = 2'b11
0b = Daisy chain clock
1b = TX_TCLK for test modes
10b = ANA Test clock
11b = clkout_out_1p0v_sl from digital
1-0clkout_ana_mux_ctrlR/W0b Selects the signal to be sent out on CLKOUT pin Automatically selects output from digital if Pin6(LED_1) is strapped As daisy chain CLKOUT if(RX_D3_strap == 1) reset_val = 2'b11 else reset_val = 2'b00
0b = Daisy chain clock
1b = TX_TCLK for test modes
10b = ANA Test clock
11b = clkout_out_1p0v_sl from digital

8.6.2.49 PCS_CTRL_1 Register (Address = 485h) [Reset = 1078h]

PCS_CTRL_1 is shown in Figure 8-68 and described in Table 8-75.

Return to the Summary Table.

Figure 8-68 PCS_CTRL_1 Register
15141312111098
RESERVEDcfg_force_slave_phase1_donecfg_dis_ipg_scr_lock_checkcfg_link_controlRESERVEDcfg_desc_first_lock_count
R-0bR/W-0bR/W-0bR/W-1bR-0bR/W-1111000b
76543210
cfg_desc_first_lock_count
R/W-1111000b
Table 8-75 PCS_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0b Reserved
14cfg_force_slave_phase1_doneR/W0b Force to say phase1 of DSP slave training done
13cfg_dis_ipg_scr_lock_checkR/W0b Disable scrambler lock check during IPG
11-9RESERVEDR0b Reserved
8-0cfg_desc_first_lock_countR/W1111000b Number of idle symbols to decide on scrambler lock

8.6.2.50 PCS_CTRL_2 Register (Address = 486h) [Reset = 0A05h]

PCS_CTRL_2 is shown in Figure 8-69 and described in Table 8-76.

Return to the Summary Table.

Figure 8-69 PCS_CTRL_2 Register
15141312111098
cfg_desc_error_count
R/W-1010b
76543210
RESERVEDcfg_rem_rcvr_sts_error_cnt
R-0bR/W-101b
Table 8-76 PCS_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
15-8cfg_desc_error_countR/W1010b Number of non-idle ymbols to look for to say scrambler unlocked
7-5RESERVEDR0b Reserved
4-0cfg_rem_rcvr_sts_error_cntR/W101b No of error symbols to rem rcvr status to go low

8.6.2.51 TX_INTER_CFG Register (Address = 489h) [Reset = 0001h]

TX_INTER_CFG is shown in Figure 8-70 and described in Table 8-77.

Return to the Summary Table.

Figure 8-70 TX_INTER_CFG Register
15141312111098
RESERVED
R-0b
76543210
RESERVEDcfg_force_tx_interleavecfg_tx_interleave_encfg_interleave_det_en
R-0bR/W-0bR/W-0bR/W-1b
Table 8-77 TX_INTER_CFG Register Field Descriptions
BitFieldTypeResetDescription
15-3RESERVEDR0b Reserved
2cfg_force_tx_interleaveR/W0b Force interleave on Tx
1cfg_tx_interleave_enR/W0b Enable interleave on tx, if interleave detected on the Rx
0b = Interleave on Tx disabled
1b = Interleave on Tx enabled if interleave detected on Rx
0cfg_interleave_det_enR/W1b Enable interleave detection
0b = Disable Interleave Detection
1b = Enable Interleave Detection

8.6.2.52 JABBER_CFG Register (Address = 496h) [Reset = 044Ch]

JABBER_CFG is shown in Figure 8-71 and described in Table 8-78.

Return to the Summary Table.

Figure 8-71 JABBER_CFG Register
15141312111098
RESERVEDcfg_rcv_jab_timer_val
R-0bR/W-10001001100b
76543210
cfg_rcv_jab_timer_val
R/W-10001001100b
Table 8-78 JABBER_CFG Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR0b Reserved
10-0cfg_rcv_jab_timer_valR/W10001001100b Jabber timeout count in usec

8.6.2.53 TEST_MODE_CTRL Register (Address = 497h) [Reset = 01C0h]

TEST_MODE_CTRL is shown in Figure 8-72 and described in Table 8-79.

Return to the Summary Table.

Figure 8-72 TEST_MODE_CTRL Register
15141312111098
RESERVEDcfg_test_mode1_symbol_cnt
R-0bR/W-11100b
76543210
cfg_test_mode1_symbol_cntRESERVED
R/W-11100bR-0b
Table 8-79 TEST_MODE_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0b Reserved
9-4cfg_test_mode1_symbol_cntR/W11100b number of +1/-1 symbols to send in test_mode_1 N= 2 + 2* CFG_TEST_MODE1_SYMBOL_CNT
3-0RESERVEDR0b Reserved

8.6.2.54 RXF_CFG Register (Address = 4A0h) [Reset = 1000h]

RXF_CFG is shown in Figure 8-73 and described in Table 8-80.

Return to the Summary Table.

Figure 8-73 RXF_CFG Register
15141312111098
bits_nibbles_swapsfd_byteRESERVEDRESERVEDRESERVEDRESERVED
R/W-0bR/W-0bR/W-1bR/W-0bR/W-0bR/W-0b
76543210
enhanced_mac_supportRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR-0bR/W-0b
Table 8-80 RXF_CFG Register Field Descriptions
BitFieldTypeResetDescription
15-14bits_nibbles_swapR/W0b Option to swap bits / nibbles inside every RX data byte
0b = regular order, no swaps - RXD[3-0]
1b = swap bits order - RXD[0-3]
1010b = swap nibbles order - { RXD[3-0] , RXD[7-4] }
1011b = swap bits order in each nibble - { RXD[4-7] , RXD[0-3] }
13sfd_byteR/W0b 0 - SFD is 0xD5 (i.e. RXF module searchs 0xD5) 1 - SFD is 0x5D (i.e. RXF module searchs 0x5D)
0b = SFD is 0xD5 (i.e. RXF module searchs 0xD5)
1b = SFD is 0x5D (i.e. RXF module searchs 0x5D)
12RESERVEDR/W1b Reserved
11RESERVEDR/W0b Reserved
10-9RESERVEDR/W0b Reserved
8RESERVEDR/W0b Reserved
7enhanced_mac_supportR/W0b Enables enhanced RX features. This bit shall be set when using wakeup abilities, CRC check or RX 1588 indication
6RESERVEDR/W0b Reserved
5RESERVEDR/W0b Reserved
4RESERVEDR/W0b Reserved
3RESERVEDR/W0b Reserved
2RESERVEDR/W0b Reserved
1RESERVEDR0b Reserved
0RESERVEDR/W0b Reserved

8.6.2.55 PG_REG_4 Register (Address = 553h) [Reset = 0000h]

PG_REG_4 is shown in Figure 8-74 and described in Table 8-81.

Return to the Summary Table.

Figure 8-74 PG_REG_4 Register
15141312111098
RESERVEDforce_pol_enforce_pol_valRESERVED
R/W-0bR/W-0bR/W-0bR/W-0b
76543210
RESERVED
R/W-0b
Table 8-81 PG_REG_4 Register Field Descriptions
BitFieldTypeResetDescription
15-14RESERVEDR/W0b Reserved
13force_pol_enR/W0b Enable force on polarity
0b = Auto-polarity on MDI
1b = Force polarity on MDI
12force_pol_valR/W0b Polarity force value. Only valid if bit [13] is 1.
0b = Forced Normal polarity
1b = Forced Inverted polarity
11-0RESERVEDR/W0b Reserved

8.6.2.56 TC1_CFG_RW Register (Address = 560h) [Reset = 07E4h]

TC1_CFG_RW is shown in Figure 8-75 and described in Table 8-82.

Return to the Summary Table.

Figure 8-75 TC1_CFG_RW Register
15141312111098
RESERVEDRESERVEDcfg_link_status_metriccfg_link_failure_multihot
R-0bR/W-0bR/W-0bR/W-111111b
76543210
cfg_link_failure_multihotcfg_comm_timer_thrscfg_bad_sqi_thrs
R/W-111111bR/W-0bR/W-100b
Table 8-82 TC1_CFG_RW Register Field Descriptions
BitFieldTypeResetDescription
15-14RESERVEDR0b Reserved
13RESERVEDR/W0b Reserved
4-3cfg_comm_timer_thrsR/W0b selects the hysteresis timer value for TC1 comm ready
0b = 2ms
1b = 500us
10b = 1ms
11b = 4ms
2-0cfg_bad_sqi_thrsR/W100b SQI threshold used to increment Link Failure Count defined by TC1. Whenever SQI becomes worse than the threshold, link failure count (Register 0x0561 bit[9:0]) as defined by TC1 is incremented

TC1_LINK_FAIL_LOSS is shown in Figure 8-76 and described in Table 8-83.

Return to the Summary Table.

Figure 8-76 TC1_LINK_FAIL_LOSS Register
Table 8-83 TC1_LINK_FAIL_LOSS Register Field Descriptions

TC1_LINK_TRAINING_TIME is shown in Figure 8-77 and described in Table 8-84.

Return to the Summary Table.

Figure 8-77 TC1_LINK_TRAINING_TIME Register
Table 8-84 TC1_LINK_TRAINING_TIME Register Field Descriptions

8.6.2.59 RGMII_CTRL Register (Address = 600h) [Reset = 0030h]

RGMII_CTRL is shown in Figure 8-78 and described in Table 8-85.

Return to the Summary Table.

Figure 8-78 RGMII_CTRL Register
15141312111098
RESERVED
R-0b
76543210
RESERVEDrgmii_tx_half_full_thcfg_rgmii_eninv_rgmii_txdinv_rgmii_rxdsup_tx_err_fd_rgmii
R-0bR/W-11bR/W-0bR/W-0bR/W-0bR/W-0b
Table 8-85 RGMII_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15-7RESERVEDR0b Reserved
6-4rgmii_tx_half_full_thR/W11b RGMII TX sync FIFO half full threshold in number if nibbles
3cfg_rgmii_enR/W0b RGMII enable bit Default from strap if(RX_D2_strap == 1) reset_val = 1 else reset_val = 0
0b = RGMII disable
1b = RGMII enable
2inv_rgmii_txdR/W0b Invert RGMII Tx wire order - full swap [3:0] -- [0:3]
1inv_rgmii_rxdR/W0b Invert RGMII Rx wire order - full swap [3:0] -- [0:3]
0sup_tx_err_fd_rgmiiR/W0b this bit can disable the TX_ERR indication input

8.6.2.60 RGMII_FIFO_STATUS Register (Address = 601h) [Reset = 0000h]

RGMII_FIFO_STATUS is shown in Figure 8-79 and described in Table 8-86.

Return to the Summary Table.

Figure 8-79 RGMII_FIFO_STATUS Register
15141312111098
RESERVED
R-0b
76543210
RESERVEDrgmii_tx_af_full_errrgmii_tx_af_empty_err
R-0bR-0bR-0b
Table 8-86 RGMII_FIFO_STATUS Register Field Descriptions
BitFieldTypeResetDescription
15-2RESERVEDR0b Reserved
1rgmii_tx_af_full_errR0b RGMII Tx fifo full error
0rgmii_tx_af_empty_errR0b RGMII Tx fifo empty error

8.6.2.61 RGMII_CLK_SHIFT_CTRL Register (Address = 602h) [Reset = 0000h]

RGMII_CLK_SHIFT_CTRL is shown in Figure 8-80 and described in Table 8-87.

Return to the Summary Table.

Figure 8-80 RGMII_CLK_SHIFT_CTRL Register
15141312111098
RESERVED
R-0b
76543210
RESERVEDcfg_rgmii_rx_clk_shift_selcfg_rgmii_tx_clk_shift_sel
R-0bR/W-0bR/W-0b
Table 8-87 RGMII_CLK_SHIFT_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15-2RESERVEDR0b Reserved
1cfg_rgmii_rx_clk_shift_selR/W0b 0: clock and data are aligned 1: clock on PIN is delayed by 90 degrees relative to RGMII_RX data if({RX_D2_strap, RX_D1_strap} == 2'b11) reset_val = 1 else resett_val = 0
0b = clock and data are aligned
1b = clock on PIN is delayed by 90 degrees relative to RGMII_RX data
0cfg_rgmii_tx_clk_shift_selR/W0b use this mode when RGMII_TX_CLK and RGMII_TXD are aligned if({RX_D2_strap, RX_D1_strap, RX_D0_strap} == 3'b101) reset_val = 1 else if({RX_D2_strap, RX_D1_strap, RX_D0_strap} == 3'b110) reset_val = 1 else reset_val = 0

8.6.2.62 RGMII_EEE_CTRL Register (Address = 603h) [Reset = 0000h]

RGMII_EEE_CTRL is shown in Figure 8-81 and described in Table 8-88.

Return to the Summary Table.

Figure 8-81 RGMII_EEE_CTRL Register
15141312111098
RESERVED
R-0b
76543210
RESERVEDcfg_rgmii_wake_signaling_en
R-0bR/W-0b
Table 8-88 RGMII_EEE_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15-2RESERVEDR0b Reserved
1-0cfg_rgmii_wake_signaling_enR/W0b RGMII signaling behavior during exit LPI period.
Bit[1] - exhibit rx_err on rx_ctrl for lpi_exit, else rx_ctrl is zero for both lpi and exit_lpi periods.
Bit[0] - exhibit zeros on rxd for lpi_exit, else rxd=IB_code
Note: option 00b is not supported, non-valid coding.

8.6.2.63 SGMII_CTRL_1 Register (Address = 608h) [Reset = 007Bh]

SGMII_CTRL_1 is shown in Figure 8-82 and described in Table 8-89.

Return to the Summary Table.

Figure 8-82 SGMII_CTRL_1 Register
15141312111098
sgmii_tx_err_discfg_align_idx_force_encfg_align_idx_valuecfg_sgmii_encfg_sgmii_rx_pol_invert
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
76543210
cfg_sgmii_tx_pol_invertserdes_tx_bits_orderserdes_rx_bits_ordercfg_sgmii_align_pkt_ensgmii_autoneg_timersgmii_autoneg_en
R/W-0bR/W-11bR/W-1bR/W-1bR/W-1bR/W-1b
Table 8-89 SGMII_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
15sgmii_tx_err_disR/W0b SGMII TX err disable bit
14cfg_align_idx_force_enR/W0b Force word boundray index selection
13-10cfg_align_idx_valueR/W0b when cfg_align_idx_force is set,This value set the iword boundray index
9cfg_sgmii_enR/W0b SGMII enable bit Default from strap if({RX_D2_strap, RX_D1_strap, RX_D0_strap} == 3'b000) reset_val = 1 else reset_val = 0
0b = SGMII MAC i/f disabled
1b = SGMII MAC i/f enabled
8cfg_sgmii_rx_pol_invertR/W0b SGMII RX bus invert polarity
7cfg_sgmii_tx_pol_invertR/W0b SGMII TX bus invert polarity
6-5serdes_tx_bits_orderR/W11b SERDES TX bits order (input to digital core)
4serdes_rx_bits_orderR/W1b SERDES RX bits order (output of digital core) : 0 - MSB-first (default) 1 - LSB-first (reversed order)
3cfg_sgmii_align_pkt_enR/W1b For aligning the start of read out TX packet (towards serializer) w/ tx_even pulse. To sync with the Code_Group/OSET FSM code slots. Default is '1', when using '0' we go back to Gemini code
2-1sgmii_autoneg_timerR/W1b Selects duration of SGMII Auto-Negotiation timer
0b = 1.6ms
1b = 2us
10b = 800us
11b = 11ms
0sgmii_autoneg_enR/W1b sgmii auto negotiation enable
0b = SGMII autoneg disabled
1b = SGMII autoneg enabled

8.6.2.64 SGMII_EEE_CTRL_1 Register (Address = 609h) [Reset = 0000h]

SGMII_EEE_CTRL_1 is shown in Figure 8-83 and described in Table 8-90.

Return to the Summary Table.

Figure 8-83 SGMII_EEE_CTRL_1 Register
15141312111098
cfg_sgmii_tx_tr_timer_valcfg_sgmii_tx_tq_timer_val
R/W-0bR/W-0b
76543210
cfg_sgmii_tx_tq_timer_valcfg_sgmii_tx_ts_timer_valcfg_support_non_eee_mac_sgmii_en
R/W-0bR/W-0bR/W-0b
Table 8-90 SGMII_EEE_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
15-11cfg_sgmii_tx_tr_timer_valR/W0b
10-6cfg_sgmii_tx_tq_timer_valR/W0b
5-1cfg_sgmii_tx_ts_timer_valR/W0b
0cfg_support_non_eee_mac_sgmii_enR/W0b special mode to support non sgmii eee mac in eee mode in the phy

8.6.2.65 SGMII_STATUS Register (Address = 60Ah) [Reset = 0000h]

SGMII_STATUS is shown in Figure 8-84 and described in Table 8-91.

Return to the Summary Table.

Figure 8-84 SGMII_STATUS Register
15141312111098
RESERVEDsgmii_page_receivedlink_status_1000bxsgmii_autoneg_completecfg_align_encfg_sync_status
R-0bR-0bR-0bR-0bR-0bR-0b
76543210
cfg_align_idxRESERVED
R-0bR-0b
Table 8-91 SGMII_STATUS Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR0b Reserved
12sgmii_page_receivedR0b Clear on read bit. Indicates that a new auto neg page was received
10sgmii_autoneg_completeR0b sgmii autoneg complete indication
0b = SGMII autoneg incomplete
1b = SGMII autoneg completed
9cfg_align_enR0b word boundary FSM - align indication
8cfg_sync_statusR0b word boundary FSM - sync status indication
7-4cfg_align_idxR0b word boundary index selection
3-0RESERVEDR0b Reserved

8.6.2.66 SGMII_EEE_CTRL_2 Register (Address = 60Bh) [Reset = 0005h]

SGMII_EEE_CTRL_2 is shown in Figure 8-85 and described in Table 8-92.

Return to the Summary Table.

Figure 8-85 SGMII_EEE_CTRL_2 Register
15141312111098
RESERVED
R-0b
76543210
RESERVEDcfg_sgmii_rx_quiet_timer_val
R-0bR/W-101b
Table 8-92 SGMII_EEE_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
15-4RESERVEDR0b Reserved
3-0cfg_sgmii_rx_quiet_timer_valR/W101b Configures the RX Quiet Timer Value.
Timer Value = (3100 + code*100)us

8.6.2.67 SGMII_CTRL_2 Register (Address = 60Ch) [Reset = 0024h]

SGMII_CTRL_2 is shown in Figure 8-86 and described in Table 8-93.

Return to the Summary Table.

Figure 8-86 SGMII_CTRL_2 Register
15141312111098
RESERVEDsgmii_cdr_lock_force_val
R-0bR/W-0b
76543210
sgmii_cdr_lock_force_ctrlsgmii_mr_restart_antx_half_full_thrx_half_full_th
R/W-0bRH/W1S-0bR/W-100bR/W-100b
Table 8-93 SGMII_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR0b Reserved
8sgmii_cdr_lock_force_valR/W0b SGMII cdr lock force value
7sgmii_cdr_lock_force_ctrlR/W0b SGMII cdr lock force enable
6sgmii_mr_restart_anRH/W1S0b Restart sgmii autonegotiation
5-3tx_half_full_thR/W100b SGMII TX sync FIFO half full threshold
2-0rx_half_full_thR/W100b SGMII RX sync FIFO half full threshold

8.6.2.68 SGMII_FIFO_STATUS Register (Address = 60Dh) [Reset = 0000h]

SGMII_FIFO_STATUS is shown in Figure 8-87 and described in Table 8-94.

Return to the Summary Table.

Figure 8-87 SGMII_FIFO_STATUS Register
15141312111098
RESERVED
R-0b
76543210
RESERVEDsgmii_rx_af_full_errsgmii_rx_af_empty_errsgmii_tx_af_full_errsgmii_tx_af_empty_err
R-0bH-0bH-0bH-0bH-0b
Table 8-94 SGMII_FIFO_STATUS Register Field Descriptions
BitFieldTypeResetDescription
15-4RESERVEDR0b Reserved
3sgmii_rx_af_full_errH0b SGMII RX fifo full error
0b = No error indication
1b = SGMII RX fifo full error has been indicated
2sgmii_rx_af_empty_errH0b SGMII RX fifo empty error
0b = No error indication
1b = SGMII RX fifo empty error has been indicated
1sgmii_tx_af_full_errH0b SGMII TX fifo full error
0b = No error indication
1b = SGMII TX fifo full error has been indicated
0sgmii_tx_af_empty_errH0b SGMII TX fiff empty error
0b = No error indication
1b = SGMII TX fifo empty error has been indicated

8.6.2.69 PRBS_STATUS_1 Register (Address = 618h) [Reset = 0000h]

PRBS_STATUS_1 is shown in Figure 8-88 and described in Table 8-95.

Return to the Summary Table.

Figure 8-88 PRBS_STATUS_1 Register
15141312111098
RESERVED
R-0b
76543210
prbs_err_ov_cnt
R-0b
Table 8-95 PRBS_STATUS_1 Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR0b Reserved
7-0prbs_err_ov_cntR0b Holds number of error counter overflow that received by the PRBS checker. Value in this register is locked when write is done to register 0x001B bit[0] or bit[1]. Counter stops on 0xFF. Note: when PRBS counters work in single mode, overflow counter is not active

8.6.2.70 PRBS_CTRL_1 Register (Address = 619h) [Reset = 0574h]

PRBS_CTRL_1 is shown in Figure 8-89 and described in Table 8-96.

Return to the Summary Table.

Figure 8-89 PRBS_CTRL_1 Register
15141312111098
RESERVEDcfg_pkt_gen_64send_pktRESERVEDcfg_prbs_chk_sel
R-0bR/W-0bRH/W1S-0bR-0bR/W-101b
76543210
RESERVEDcfg_prbs_gen_selcfg_prbs_cnt_modecfg_prbs_chk_enablecfg_pkt_gen_prbspkt_gen_en
R-0bR/W-111bR/W-0bR/W-1bR/W-0bR/W-0b
Table 8-96 PRBS_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
15-14RESERVEDR0b Reserved
13cfg_pkt_gen_64R/W0b
0b = Transmit 1518 byte packets in packet generation mode
1b = Transmit 64 byte packets in packet generation mode
12send_pktRH/W1S0b Enables generating MAC packet with fix/incremental data w CRC (pkt_gen_en has to be set and cfg_pkt_gen_prbs has to be clear) Cleared automatically when pkt_done is set
11RESERVEDR0b Reserved
10-8cfg_prbs_chk_selR/W101b 000 : Checker receives from RGMII TX
001 : Checker receives from SGMII TX
010 : Checker receives from RMII RX
011 : Checker receives from MII
101 : Checker receives from Cu RX
110 : Reserved
111 : Reserved
7RESERVEDR0b Reserved
6-4cfg_prbs_gen_selR/W111b 000 : PRBS transmits to RGMII RX
001 : PRBS transmits to SGMII RX
010 : PRBS transmits to RMII RX
011 : PRBS transmits to MII RX
101 : PRBS transmits to Cu TX
110 : Reserved
111 : Reserved
3cfg_prbs_cnt_modeR/W0b
0b = Single mode, When one of the PRBS counters reaches max value, PRBS checker stops counting.
1b = Continuous mode, when one of the PRBS counters reaches max value, pulse is generated and counter starts counting from zero again
2cfg_prbs_chk_enableR/W1b Enable PRBS checker
1cfg_pkt_gen_prbsR/W0b If set: (1) When pkt_gen_en is set, PRBS packets are generated continuously (3) When pkt_gen_en is cleared, PRBS RX checker is still enabled If cleared: (1) When pkt_gen_en is set, non - PRBS packet is generated (3) When pkt_gen_en is cleared, PRBS RX checker is disabled as well
0pkt_gen_enR/W0b Enable/disable for prbs/packet generator
0b = Disable for prbs/packet generator
1b = Enable for prbs/packet generator

8.6.2.71 PRBS_CTRL_2 Register (Address = 61Ah) [Reset = 05DCh]

PRBS_CTRL_2 is shown in Figure 8-90 and described in Table 8-97.

Return to the Summary Table.

Figure 8-90 PRBS_CTRL_2 Register
15141312111098
cfg_pkt_len_prbs
R/W-10111011100b
76543210
cfg_pkt_len_prbs
R/W-10111011100b
Table 8-97 PRBS_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
15-0cfg_pkt_len_prbsR/W10111011100b Length (in bytes) of PRBS packets and MAC packets w CRC

8.6.2.72 PRBS_CTRL_3 Register (Address = 61Bh) [Reset = 007Dh]

PRBS_CTRL_3 is shown in Figure 8-91 and described in Table 8-98.

Return to the Summary Table.

Figure 8-91 PRBS_CTRL_3 Register
15141312111098
RESERVED
R-0b
76543210
cfg_ipg_len
R/W-1111101b
Table 8-98 PRBS_CTRL_3 Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR0b Reserved
7-0cfg_ipg_lenR/W1111101b Inter-packet gap (in bytes) between packets

8.6.2.73 PRBS_STATUS_2 Register (Address = 61Ch) [Reset = 0000h]

PRBS_STATUS_2 is shown in Figure 8-92 and described in Table 8-99.

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Figure 8-92 PRBS_STATUS_2 Register
15141312111098
prbs_byte_cnt
R-0b
76543210
prbs_byte_cnt
R-0b
Table 8-99 PRBS_STATUS_2 Register Field Descriptions
BitFieldTypeResetDescription
15-0prbs_byte_cntR0b Holds number of total bytes that received by the PRBS checker. Value in this register is locked when write is done to register 0x001B bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFF

8.6.2.74 PRBS_STATUS_3 Register (Address = 61Dh) [Reset = 0000h]

PRBS_STATUS_3 is shown in Figure 8-93 and described in Table 8-100.

Return to the Summary Table.

Figure 8-93 PRBS_STATUS_3 Register
15141312111098
prbs_pkt_cnt_15_0
R-0b
76543210
prbs_pkt_cnt_15_0
R-0b
Table 8-100 PRBS_STATUS_3 Register Field Descriptions
BitFieldTypeResetDescription
15-0prbs_pkt_cnt_15_0R0b Bits [15:0] of number of total packets received by the PRBS checker Value in this register is locked when write is done to register 0x001B bit[15] or bit[14]. When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF

8.6.2.75 PRBS_STATUS_4 Register (Address = 61Eh) [Reset = 0000h]

PRBS_STATUS_4 is shown in Figure 8-94 and described in Table 8-101.

Return to the Summary Table.

Figure 8-94 PRBS_STATUS_4 Register
15141312111098
prbs_pkt_cnt_31_16
R-0b
76543210
prbs_pkt_cnt_31_16
R-0b
Table 8-101 PRBS_STATUS_4 Register Field Descriptions
BitFieldTypeResetDescription
15-0prbs_pkt_cnt_31_16R0b Bits [31:16] of number of total packets received by the PRBS checker Value in this register is locked when write is done to register 0x001B bit[15] or bit[14]. When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF

8.6.2.76 PRBS_STATUS_5 Register (Address = 620h) [Reset = 0000h]

PRBS_STATUS_5 is shown in Figure 8-95 and described in Table 8-102.

Return to the Summary Table.

Figure 8-95 PRBS_STATUS_5 Register
15141312111098
RESERVEDpkt_donepkt_gen_busyprbs_pkt_ovprbs_byte_ovprbs_lock
R-0bR-0bR-0bR-0bR-0bR-0b
76543210
prbs_err_cnt
R-0b
Table 8-102 PRBS_STATUS_5 Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR0b Reserved
12pkt_doneR0b Set when all MAC packets w CRC are transmitted
11pkt_gen_busyR0b status of packet generator
10prbs_pkt_ovR0b If set, packet counter reached overflow Overflow is cleared when PRBS counters are cleared - done by setting bit[15] of 0x001B
9prbs_byte_ovR0b If set, bytes counter reached overflow Overflow is cleared when PRBS counters are cleared - done by setting bit[15] of 0x001B
8prbs_lockR0b prbs lock status
7-0prbs_err_cntR0b Holds number of errored bytes that received by the PRBS checker Value in this register is locked when write is done to bit[0] or bit[1] When PRBS Count Mode set to zero, count stops on 0xFF Notes: Writing bit 0 generates a lock signal for the PRBS counters. Writing bit 1 generates a lock and clear signal for the PRBS counters

8.6.2.77 PRBS_STATUS_6 Register (Address = 622h) [Reset = 0000h]

PRBS_STATUS_6 is shown in Figure 8-96 and described in Table 8-103.

Return to the Summary Table.

Figure 8-96 PRBS_STATUS_6 Register
15141312111098
pkt_err_cnt_15_0
R-0b
76543210
pkt_err_cnt_15_0
R-0b
Table 8-103 PRBS_STATUS_6 Register Field Descriptions
BitFieldTypeResetDescription
15-0pkt_err_cnt_15_0R0b bits [15:0] of counter which records number or PRBS erroneous bytes received. This field gets cleared when bit[15] or bit[14] is written as 1 to register 0x001B

8.6.2.78 PRBS_STATUS_7 Register (Address = 623h) [Reset = 0000h]

PRBS_STATUS_7 is shown in Figure 8-97 and described in Table 8-104.

Return to the Summary Table.

Figure 8-97 PRBS_STATUS_7 Register
15141312111098
pkt_err_cnt_31_16
R-0b
76543210
pkt_err_cnt_31_16
R-0b
Table 8-104 PRBS_STATUS_7 Register Field Descriptions
BitFieldTypeResetDescription
15-0pkt_err_cnt_31_16R0b bits [31:16] of counter which records number or PRBS erroneous bytes received. This field gets cleared when bit[15] or bit[14] is written as 1 to register 0x001B

8.6.2.79 PRBS_CTRL_4 Register (Address = 624h) [Reset = 5511h]

PRBS_CTRL_4 is shown in Figure 8-98 and described in Table 8-105.

Return to the Summary Table.

Figure 8-98 PRBS_CTRL_4 Register
15141312111098
cfg_pkt_data
R/W-1010101b
76543210
cfg_pkt_modecfg_pattern_vld_bytescfg_pkt_cnt
R/W-0bR/W-10bR/W-1b
Table 8-105 PRBS_CTRL_4 Register Field Descriptions
BitFieldTypeResetDescription
15-8cfg_pkt_dataR/W1010101b Fixed data to be sent in Fix data mode
7-6cfg_pkt_modeR/W0b Selects the type of data sent
0b = Incremental Data
1b = Fixed Data
10b = PRBS Data (Random Data)
11b = PRBS Data (Random Data)
5-3cfg_pattern_vld_bytesR/W10b Number of bytes of valid pattern in packet (Max - 6)
2-0cfg_pkt_cntR/W1b Configures the number of MAC packets to be transmitted by packet generator
0b = 1 packet
1b = 10 packets
10b = 100 packets
11b = 1000 packets
100b = 10000 packets
101b = 100000 packets
110b = 1000000 packets
111b = Continuous packets

8.6.2.80 PATTERN_CTRL_1 Register (Address = 625h) [Reset = 0000h]

PATTERN_CTRL_1 is shown in Figure 8-99 and described in Table 8-106.

Return to the Summary Table.

Figure 8-99 PATTERN_CTRL_1 Register
15141312111098
pattern_15_0
R/W-0b
76543210
pattern_15_0
R/W-0b
Table 8-106 PATTERN_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
15-0pattern_15_0R/W0b Bits 15:0 of pattern

8.6.2.81 PATTERN_CTRL_2 Register (Address = 626h) [Reset = 0000h]

PATTERN_CTRL_2 is shown in Figure 8-100 and described in Table 8-107.

Return to the Summary Table.

Figure 8-100 PATTERN_CTRL_2 Register
15141312111098
pattern_31_16
R/W-0b
76543210
pattern_31_16
R/W-0b
Table 8-107 PATTERN_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
15-0pattern_31_16R/W0b Bits 31:16 of pattern

8.6.2.82 PATTERN_CTRL_3 Register (Address = 627h) [Reset = 0000h]

PATTERN_CTRL_3 is shown in Figure 8-101 and described in Table 8-108.

Return to the Summary Table.

Figure 8-101 PATTERN_CTRL_3 Register
15141312111098
pattern_47_32
R/W-0b
76543210
pattern_47_32
R/W-0b
Table 8-108 PATTERN_CTRL_3 Register Field Descriptions
BitFieldTypeResetDescription
15-0pattern_47_32R/W0b Bits 47:32 of pattern

8.6.2.83 PMATCH_CTRL_1 Register (Address = 628h) [Reset = 0000h]

PMATCH_CTRL_1 is shown in Figure 8-102 and described in Table 8-109.

Return to the Summary Table.

Figure 8-102 PMATCH_CTRL_1 Register
15141312111098
pmatch_data_15_0
R/W-0b
76543210
pmatch_data_15_0
R/W-0b
Table 8-109 PMATCH_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
15-0pmatch_data_15_0R/W0b Bits 15:0 of Perfect Match Data - used for DA (destination address) match

8.6.2.84 PMATCH_CTRL_2 Register (Address = 629h) [Reset = 0000h]

PMATCH_CTRL_2 is shown in Figure 8-103 and described in Table 8-110.

Return to the Summary Table.

Figure 8-103 PMATCH_CTRL_2 Register
15141312111098
pmatch_data_31_16
R/W-0b
76543210
pmatch_data_31_16
R/W-0b
Table 8-110 PMATCH_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
15-0pmatch_data_31_16R/W0b Bits 31:16 of Perfect Match Data - used for DA (destination address) match

8.6.2.85 PMATCH_CTRL_3 Register (Address = 62Ah) [Reset = 0000h]

PMATCH_CTRL_3 is shown in Figure 8-104 and described in Table 8-111.

Return to the Summary Table.

Figure 8-104 PMATCH_CTRL_3 Register
15141312111098
pmatch_data_47_32
R/W-0b
76543210
pmatch_data_47_32
R/W-0b
Table 8-111 PMATCH_CTRL_3 Register Field Descriptions
BitFieldTypeResetDescription
15-0pmatch_data_47_32R/W0b Bits 47:32 of Perfect Match Data - used for DA (destination address) match

8.6.2.86 TX_PKT_CNT_1 Register (Address = 639h) [Reset = 0000h]

TX_PKT_CNT_1 is shown in Figure 8-105 and described in Table 8-112.

Return to the Summary Table.

Figure 8-105 TX_PKT_CNT_1 Register
15141312111098
tx_pkt_cnt_15_0
0b
76543210
tx_pkt_cnt_15_0
0b
Table 8-112 TX_PKT_CNT_1 Register Field Descriptions
BitFieldTypeResetDescription
15-0tx_pkt_cnt_15_00b Lower 16 bits of Tx packet counter Note : Register is cleared when 0x60F, 0x610, 0x611 are read in sequence

8.6.2.87 TX_PKT_CNT_2 Register (Address = 63Ah) [Reset = 0000h]

TX_PKT_CNT_2 is shown in Figure 8-106 and described in Table 8-113.

Return to the Summary Table.

Figure 8-106 TX_PKT_CNT_2 Register
15141312111098
tx_pkt_cnt_31_16
0b
76543210
tx_pkt_cnt_31_16
0b
Table 8-113 TX_PKT_CNT_2 Register Field Descriptions
BitFieldTypeResetDescription
15-0tx_pkt_cnt_31_160b Upper 16 bits of Tx packet counter Note : Register is cleared when 0x60F, 0x610, 0x611 are read in sequence

8.6.2.88 TX_PKT_CNT_3 Register (Address = 63Bh) [Reset = 0000h]

TX_PKT_CNT_3 is shown in Figure 8-107 and described in Table 8-114.

Return to the Summary Table.

Figure 8-107 TX_PKT_CNT_3 Register
15141312111098
tx_err_pkt_cnt
0b
76543210
tx_err_pkt_cnt
0b
Table 8-114 TX_PKT_CNT_3 Register Field Descriptions
BitFieldTypeResetDescription
15-0tx_err_pkt_cnt0b Tx packet w error (CRC error) counter Note : Register is cleared when 0x60F, 0x610, 0x611 are read in sequence

8.6.2.89 RX_PKT_CNT_1 Register (Address = 63Ch) [Reset = 0000h]

RX_PKT_CNT_1 is shown in Figure 8-108 and described in Table 8-115.

Return to the Summary Table.

Figure 8-108 RX_PKT_CNT_1 Register
15141312111098
rx_pkt_cnt_15_0
0b
76543210
rx_pkt_cnt_15_0
0b
Table 8-115 RX_PKT_CNT_1 Register Field Descriptions
BitFieldTypeResetDescription
15-0rx_pkt_cnt_15_00b Lower 16 bits of Rx packet counter Note : Register is cleared when 0x612, 0x613, 0x614 are read in sequence

8.6.2.90 RX_PKT_CNT_2 Register (Address = 63Dh) [Reset = 0000h]

RX_PKT_CNT_2 is shown in Figure 8-109 and described in Table 8-116.

Return to the Summary Table.

Figure 8-109 RX_PKT_CNT_2 Register
15141312111098
rx_pkt_cnt_31_16
0b
76543210
rx_pkt_cnt_31_16
0b
Table 8-116 RX_PKT_CNT_2 Register Field Descriptions
BitFieldTypeResetDescription
15-0rx_pkt_cnt_31_160b Upper 16 bits of Rx packet counter Note : Register is cleared when 0x612, 0x613, 0x614 are read in sequence

8.6.2.91 RX_PKT_CNT_3 Register (Address = 63Eh) [Reset = 0000h]

RX_PKT_CNT_3 is shown in Figure 8-110 and described in Table 8-117.

Return to the Summary Table.

Figure 8-110 RX_PKT_CNT_3 Register
15141312111098
rx_err_pkt_cnt
0b
76543210
rx_err_pkt_cnt
0b
Table 8-117 RX_PKT_CNT_3 Register Field Descriptions
BitFieldTypeResetDescription
15-0rx_err_pkt_cnt0b Rx packet w error (CRC error) counter Note : Register is cleared when 0x612, 0x613, 0x614 are read in sequence

8.6.2.92 RMII_CTRL_1 Register (Address = 648h) [Reset = 0120h]

RMII_CTRL_1 is shown in Figure 8-111 and described in Table 8-118.

Return to the Summary Table.

Figure 8-111 RMII_CTRL_1 Register
15141312111098
RESERVEDcfg_rmii_dis_delayed_txd_encfg_rmii_half_full_th
R-0bR/W-0bR/W-10b
76543210
cfg_rmii_half_full_thcfg_rmii_modecfg_rmii_bypass_afifo_encfg_xi_50RESERVEDRESERVEDcfg_rmii_rev1_0cfg_rmii_enh
R/W-10bR/W-0bR/W-1bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 8-118 RMII_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR0b Reserved
10cfg_rmii_dis_delayed_txd_enR/W0b If set, disables delay of TXD in RMII mode
9-7cfg_rmii_half_full_thR/W10b FIFO Half Full Threshold in nibbles for the RMII Rx FIFO
6cfg_rmii_modeR/W0b 1 = RMII enabled 0 = RMII disabled if({RX_D2_strap, RX_D1_strap} == 2'b01) reset_val = 1 else reset_val = 0
0b = RMII disabled
1b = RMII enabled
5cfg_rmii_bypass_afifo_enR/W1b 1= RMII async fifo bypass enable 0= RMII async fifo not bypassed
0b = RMII async fifo not bypassed
1b = RMII async fifo bypass enable
4cfg_xi_50R/W0b XI sel for RMII mode if({RX_D2_strap, RX_D1_strap, RX_D0_strap} == 3'b010) reset_val = 1 else reset_val = 0
3RESERVEDR/W0b Reserved
2RESERVEDR/W0b Reserved
1cfg_rmii_rev1_0R/W0b RMII Rev1.0 enable bit
0cfg_rmii_enhR/W0b RMII enahnced mode enable bit

8.6.2.93 RMII_STATUS_1 Register (Address = 649h) [Reset = 0000h]

RMII_STATUS_1 is shown in Figure 8-112 and described in Table 8-119.

Return to the Summary Table.

Figure 8-112 RMII_STATUS_1 Register
15141312111098
RESERVED
R-0b
76543210
RESERVEDrmii_af_unf_errrmii_af_ovf_err
R-0bR-0bR-0b
Table 8-119 RMII_STATUS_1 Register Field Descriptions
BitFieldTypeResetDescription
15-2RESERVEDR0b Reserved
1rmii_af_unf_errR0b Clear on read bit RMII fifo undeflow error status
0rmii_af_ovf_errR0b Clear on Read bit RMII fifo overflow status

8.6.2.94 RMII_OVERRIDE_CTRL Register (Address = 64Ah) [Reset = 0010h]

RMII_OVERRIDE_CTRL is shown in Figure 8-113 and described in Table 8-120.

Return to the Summary Table.

Figure 8-113 RMII_OVERRIDE_CTRL Register
15141312111098
RESERVEDcfg_clk50_tx_dllcfg_clk50_dllRESERVED
R-0bR/W-0bR/W-0bR/W-0b
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0bR/W-0bR/W-0bR/W-1bR/W-0bR/W-0bR/W-0bR/W-0b
Table 8-120 RMII_OVERRIDE_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR0b Reserved
10cfg_clk50_tx_dllR/W0b 1 = use 50M DLL clock in RMII master for TX 0 = legacy mode if({RX_D2_strap, RX_D1_strap, RX_D0_strap} == 3'b011) reset_val = 1 else reset_val = 0
0b = legacy mode
1b = use 50M DLL clock in RMII master for TX
9cfg_clk50_dllR/W0b 1 = use 50M DLL clock in RMII slave for RX 0 = use legacy mode if({RX_D2_strap, RX_D1_strap, RX_D0_strap} == 3'b010) reset_val = 1 else reset_val = 0
0b = use legacy mode
1b = use 50M DLL clock in RMII slave for RX
8RESERVEDR/W0b Reserved
7RESERVEDR/W0b Reserved
6RESERVEDR/W0b Reserved
5RESERVEDR/W0b Reserved
4RESERVEDR/W1b Reserved
3RESERVEDR/W0b Reserved
2RESERVEDR/W0b Reserved
1RESERVEDR/W0b Reserved
0RESERVEDR/W0b Reserved

8.6.2.95 dsp_reg_71 Register (Address = 871h) [Reset = 0000h]

dsp_reg_71 is shown in Figure 8-114 and described in Table 8-121.

Return to the Summary Table.

Figure 8-114 dsp_reg_71 Register
15141312111098
RESERVED
R-0b
76543210
worst_sqi_outRESERVEDsqi_outRESERVED
0bR-0bR-0bR-0b
Table 8-121 dsp_reg_71 Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR0b Reserved
7-5worst_sqi_out0b Worst SQI value since last read
4RESERVEDR0b Reserved
3-1sqi_outR0b SQI value
0RESERVEDR0b Reserved

8.6.2.96 MMD1_PMA_CTRL_1 Register (Address = 1000h) [Reset = 0000h]

MMD1_PMA_CTRL_1 is shown in Figure 8-115 and described in Table 8-122.

Return to the Summary Table.

Figure 8-115 MMD1_PMA_CTRL_1 Register
15141312111098
PMA_resetRESERVED
R/W-0bR-0b
76543210
RESERVEDPMA_loopback
R-0bR/W-0b
Table 8-122 MMD1_PMA_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
15PMA_resetR/W0b 0 = PMA not reset 1= PMA reset
0b = PMA not reset
1b = PMA reset
14-1RESERVEDR0b Reserved
0PMA_loopbackR/W0b 0 = PMA loopback not set 1= PMA loopback set
0b = PMA loopback not set
1b = PMA loopback set

8.6.2.97 MMD1_PMA_STATUS_1 Register (Address = 1001h) [Reset = 0000h]

MMD1_PMA_STATUS_1 is shown in Figure 8-116 and described in Table 8-123.

Return to the Summary Table.

Figure 8-116 MMD1_PMA_STATUS_1 Register
15141312111098
RESERVED
R-0b
76543210
RESERVEDlink_statusRESERVED
R-0bR-0bR-0b
Table 8-123 MMD1_PMA_STATUS_1 Register Field Descriptions
BitFieldTypeResetDescription
15-3RESERVEDR0b Reserved
1-0RESERVEDR0b Reserved

8.6.2.98 MMD1_PMA_STAUS_2 Register (Address = 1007h) [Reset = 003Dh]

MMD1_PMA_STAUS_2 is shown in Figure 8-117 and described in Table 8-124.

Return to the Summary Table.

Figure 8-117 MMD1_PMA_STAUS_2 Register
15141312111098
RESERVED
R-0b
76543210
RESERVEDPMA/PMD type selection
R-0bR-111101b
Table 8-124 MMD1_PMA_STAUS_2 Register Field Descriptions
BitFieldTypeResetDescription
15-6RESERVEDR0b Reserved
5-0PMA/PMD type selectionR111101b PMA or PMD type selection field
11111xb = reserved for future use
111100b = reserved for future use
1110xxb = reserved for future use
110xxxb = reserved for future use
111101b = 100BASE-T1 PMA or PMD

8.6.2.99 MMD1_PMA_EXT_ABILITY_1 Register (Address = 100Bh) [Reset = 0800h]

MMD1_PMA_EXT_ABILITY_1 is shown in Figure 8-118 and described in Table 8-125.

Return to the Summary Table.

Figure 8-118 MMD1_PMA_EXT_ABILITY_1 Register
15141312111098
RESERVEDBASE-T1 extended abilitiesRESERVED
R-0bR-1bR-0b
76543210
RESERVED
R-0b
Table 8-125 MMD1_PMA_EXT_ABILITY_1 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0b Reserved
11BASE-T1 extended abilitiesR1b 1 = PMA/PMD has BASE-T1 extended abilities listed in register 18 in MMD1 0 = PMA/PMD does not have BASE-T1 extended abilities
0b = PMA/PMD does not have BASE-T1 extended abilities
1b = PMA/PMD has BASE-T1 extended abilities listed in register 18 in MMD1
10-0RESERVEDR0b Reserved

8.6.2.100 MMD1_PMA_EXT_ABILITY_2 Register (Address = 1012h) [Reset = 0001h]

MMD1_PMA_EXT_ABILITY_2 is shown in Figure 8-119 and described in Table 8-126.

Return to the Summary Table.

Figure 8-119 MMD1_PMA_EXT_ABILITY_2 Register
15141312111098
RESERVED
R-0b
76543210
RESERVED100BASE-T1 ability
R-0bR-1b
Table 8-126 MMD1_PMA_EXT_ABILITY_2 Register Field Descriptions
BitFieldTypeResetDescription
15-1RESERVEDR0b Reserved
0100BASE-T1 abilityR1b 1 = PMA/PMD is able to perform 100BASE-T1 0 = PMA/PMD is not able to perform 100BASE-T1
0b = PMA/PMD is not able to perform 100BASE-T1
1b = PMA/PMD is able to perform 100BASE-T1

8.6.2.101 MMD1_PMA_CTRL_2 Register (Address = 1834h) [Reset = 8000h]

MMD1_PMA_CTRL_2 is shown in Figure 8-120 and described in Table 8-127.

Return to the Summary Table.

Figure 8-120 MMD1_PMA_CTRL_2 Register
15141312111098
master_slave_man_cfg_enbrk_ms_cfgRESERVED
R-1bR/W-0bR-0b
76543210
RESERVEDtype selection
R-0bR-0b
Table 8-127 MMD1_PMA_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
15master_slave_man_cfg_enR1b Value always 1
14brk_ms_cfgR/W0b 1 = Configure PHY as MASTER 0 = Configure PHY as SLAVE pkg_36: reset_val = LED_0_strap pkg_28: reset_val = RX_D3_strap
0b = Configure PHY as SLAVE
1b = Configure PHY as MASTER
13-4RESERVEDR0b Reserved
3-0type selectionR0b type selection field 1xxxb = Reserved for future use 01xxb = Reserved for future use 001xb = Reserved for future use 0001b = Reserved for future use
0b = 100BASE-T1

8.6.2.102 MMD1_PMA_TEST_MODE_CTRL Register (Address = 1836h) [Reset = 0000h]

MMD1_PMA_TEST_MODE_CTRL is shown in Figure 8-121 and described in Table 8-128.

Return to the Summary Table.

Figure 8-121 MMD1_PMA_TEST_MODE_CTRL Register
15141312111098
brk_test_modeRESERVED
R/W-0bR/W-0b
76543210
RESERVED
R/W-0b
Table 8-128 MMD1_PMA_TEST_MODE_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15-13brk_test_modeR/W0b 100BASE-T1 test mode control
000b = Normal mode operation
001b = Test mode 1
010b = Test mode 2
011b = Reserved
100b = Test mode 4
101b = Test mode 5
110b = Reserved
111b = Reserved
12-0RESERVEDR/W0b Reserved

8.6.2.103 MMD3_PCS_CTRL_1 Register (Address = 3000h) [Reset = 0000h]

MMD3_PCS_CTRL_1 is shown in Figure 8-122 and described in Table 8-129.

Return to the Summary Table.

Figure 8-122 MMD3_PCS_CTRL_1 Register
15141312111098
PCS_ResetPCS_loopbackRESERVEDrx_clock_stoppableRESERVED
R/W-0bR/W-0bR-0bR/W-0bR-0b
76543210
RESERVED
R-0b
Table 8-129 MMD3_PCS_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
15PCS_ResetR/W0b Reset bit, Self Clear. When write to this bit 1: 1. reset the registers (not vendor specific) at MMD3/MMD7. 2. Reset brk_top Please notice: This register is WSC (write-self-clear) and not read-only!
14PCS_loopbackR/W0b This bit is cleared by PCS_Reset
13-11RESERVEDR0b Reserved
10rx_clock_stoppableR/W0b RW, reset value = 1. 1= PHY may stop receive clock during LPI 0= Clock not stoppable Note: this flop implemented at glue logic
9-0RESERVEDR0b Reserved

8.6.2.104 MMD3_PCS_Status_1 Register (Address = 3001h) [Reset = 0000h]

MMD3_PCS_Status_1 is shown in Figure 8-123 and described in Table 8-130.

Return to the Summary Table.

Figure 8-123 MMD3_PCS_Status_1 Register
15141312111098
RESERVEDTX_LPI_receivedRX_LPI_receivedTx_LPI_indicationRx_LPI_indication
R-0bR-0bR-0bR-0bR-0b
76543210
RESERVEDtx_clock_stoppableRESERVED
R-0bR-0bR-0b
Table 8-130 MMD3_PCS_Status_1 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0b Reserved
11TX_LPI_receivedR0b RO/LH
0b = LPI not received
1b = Tx PCS hs received LPI
10RX_LPI_receivedR0b RO/LH
0b = LPI not received
1b = Rx PCS hs received LPI
9Tx_LPI_indicationR0b 1= TX PCS is currently receiving LPI 0= PCS is not currently receiving LPI
0b = PCS is not currently receiving LPI
1b = TX PCS is currently receiving LPI
8Rx_LPI_indicationR0b 1= RX PCS is currently receiving LPI 0= PCS is not currently receiving LPI
0b = PCS is not currently receiving LPI
1b = RX PCS is currently receiving LPI
7RESERVEDR0b Reserved
6tx_clock_stoppableR0b 1= the MAC may stop the clock during LPI 0= Clock not stoppable
0b = Clock not stoppable
1b = the MAC may stop the clock during LPI
5-0RESERVEDR0b Reserved