JAJSQT9A November   2023  – March 2024 DRV8242-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
    1. 5.1 HW Variant
      1. 5.1.1 VQFN (20) package
    2. 5.2 SPI Variant
      1. 5.2.1 VQFN (20) package
      2. 5.2.2 VQFN (20) package
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information VQFN-RHL package
    5. 6.5  Electrical Characteristics
    6. 6.6  Transient Thermal Impedance & Current Capability
    7. 6.7  SPI Timing Requirements
    8. 6.8  Switching Waveforms
      1. 6.8.1 Output switching transients
        1. 6.8.1.1 High-Side Recirculation
    9. 6.9  Wake-up Transients
      1. 6.9.1 HW Variant
      2. 6.9.2 SPI Variant
    10. 6.10 Fault Reaction Transients
      1. 6.10.1 Retry setting
      2. 6.10.2 Latch setting
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 HW Variant
      2. 7.2.2 SPI Variant
    3. 7.3 Feature Description
      1. 7.3.1 External Components
        1. 7.3.1.1 HW Variant
        2. 7.3.1.2 SPI Variant
      2. 7.3.2 Bridge Control
        1. 7.3.2.1 PH/EN mode
        2. 7.3.2.2 PWM mode
        3. 7.3.2.3 Register - Pin Control - SPI Variant Only
      3. 7.3.3 Device Configuration
        1. 7.3.3.1 Slew Rate (SR)
        2. 7.3.3.2 IPROPI
        3. 7.3.3.3 ITRIP Regulation
        4. 7.3.3.4 DIAG
          1. 7.3.3.4.1 HW variant
          2. 7.3.3.4.2 SPI variant
      4. 7.3.4 Protection and Diagnostics
        1. 7.3.4.1 Over Current Protection (OCP)
        2. 7.3.4.2 Over Temperature Protection (TSD)
        3. 7.3.4.3 Off-State Diagnostics (OLP)
        4. 7.3.4.4 On-State Diagnostics (OLA) - SPI Variant Only
        5. 7.3.4.5 VM Over Voltage Monitor
        6. 7.3.4.6 VM Under Voltage Monitor
        7. 7.3.4.7 Power On Reset (POR)
        8. 7.3.4.8 Event Priority
    4. 7.4 Device Functional States
      1. 7.4.1 SLEEP State
      2. 7.4.2 STANDBY State
      3. 7.4.3 Wake-up to STANDBY State
      4. 7.4.4 ACTIVE State
      5. 7.4.5 nSLEEP Reset Pulse (HW Variant, LATCHED setting Only)
    5. 7.5 Programming - SPI Variant Only
      1. 7.5.1 SPI Interface
      2. 7.5.2 Standard Frame
      3. 7.5.3 SPI Interface for Multiple Peripherals
        1. 7.5.3.1 Daisy Chain Frame for Multiple Peripherals
  9. 8 Register Map - SPI Variant Only
    1. 8.1 User Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Load Summary
    2. 9.2 Typical Application
      1. 9.2.1 HW Variant
      2. 9.2.2 SPI Variant
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Bulk Capacitance Sizing
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1 User Registers

The following table lists all the registers that can be accessed by the user. All register addresses NOT listed in this table should be considered as "reserved" locations and access is blocked to this space. Accessing them will cause a SPI_ERR.

Table 8-1 User Registers
NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Type (2)Addr
DEVICE_IDDEV_ID[5]DEV_ID[4]DEV_ID[3]DEV_ID[2]DEV_ID[1]DEV_ID[0]REV_ID[1]REV_ID[0]R00h
FAULT_SUMMARYSPI_ERR(3)PORFAULTVMOVVMUVOCPTSDOLA(3)R01h
STATUS1OLA1OLA2ITRIP_CMPACTIVEOCP_H1OCP_L1OCP_H2OCP_L2R02h
STATUS2DRVOFF_STATN/A(4)N/A(4)ACTIVEN/A(4)N/A(4)N/A(4)OLP_CMPR03h
COMMANDCLR_FLTN/A(4)N/A(4)SPI_IN_LOCK[1]SPI_IN_LOCK[0] (1)N/A(4)REG_LOCK[1]REG_LOCK[0] (1)R/W08h
SPI_INN/A(4)N/A(4)N/A(4)N/A(4)S_DRVOFF (1)S_DRVOFF2(1)S_EN_IN1S_PH_IN2R/W09h
CONFIG1EN_OLAVMOV_SEL[1]VMOV_SEL[0] SSC_DIS(1)OCP_RETRYTSD_RETRYVMOV_RETRYOLA_RETRYR/W0Ah
CONFIG2PWM_EXTENDS_DIAG[1]S_DIAG[0]N/A(4)OLA_FLTRS_ITRIP[2]S_ITRIP[1]S_ITRIP[0]R/W0Bh
CONFIG3TOFF[1]TOFF[0] (1)N/A(4)S_SR[2]S_SR[1] S_SR[0] S_MODE[1]S_MODE[0]R/W0Ch
CONFIG4TOCP_SEL[1]TOCP_SEL[0]N/A(4)OCP_SEL[1]OCP_SEL[0]DRVOFF_SEL(1)EN_IN1_SELPH_IN2_SELR/W0Dh
(1) Defaulted to 1b on reset, others are defaulted to 0b on reset
(2) R = Read Only, R/W = Read/Write
(3) OLA replaced by SPI_ERR in the first SDO byte response, common to all SPI frames. Refer SDO - Standard frame format.
(4) N/A = Not available (read back of this bit will be 0b)

8.1.1 DEVICE_ID register (Address = 00h)

Return to the User Register table.

DeviceDEVICE_ID value
DRV8242S-Q1 20h
DRV8243S-Q132h
DRV8244S-Q142h
DRV8245S-Q152h
DRV8242P-Q1 24h
DRV8243P-Q136h
DRV8244P-Q146h
DRV8245P-Q156h

8.1.2 FAULT_SUMMARY Register (Address = 01h) [reset = 40h]

Return to the User Register table.

BitFieldTypeResetDescription
7SPI_ERRR0b1b indicates that a SPI communication fault has occurred in the previous SPI frame.
6PORR1b1b indicates that a power-on-reset has been detected.
5FAULTR0bLogic OR of SPI_ERR, POR, VMOV, VMUV, OCP, TSD
4VMOVR0b1b indicates that a VM over voltage has been detected. Refer VMOV_SEL to change thresholds or disable diagnostic, VMOV_RETRY to configure fault reaction.
3VMUVR0b1b indicates that a VM under voltage has been detected.
2OCPR0b1b indicates that an over current has been detected in either one or more power FETs. Refer OCP_SEL, TOCP_SEL to change thresholds & filter times. Refer OCP_RETRY to configure fault reaction.
1TSDR0b1b indicates that an over temperature has been detected. Refer TSD_RETRY to configure fault reaction.
0OLAR0b1b indicates that an open load condition has been detected in the ACTIVE state. Refer to EN_OLA to disable diagnostic, OLA_RETRY to configure fault reaction.

8.1.3 STATUS1 Register (Address = 02h) [reset = 00h]

Return to the User Register table.

BitFieldTypeResetDescription
7OLA1R0b1b indicates that an open load condition has been detected in the ACTIVE state on OUT1
6OLA2R0b1b indicates that an open load condition has been detected in the ACTIVE state on OUT2
5ITRIP_CMPR0b1b indicates that load current has reached the ITRIP regulation level.
4ACTIVER0b1b indicates that the device is in the ACTIVE state
3OCP_H1R0b1b indicates that an over current has been detected on the high-side FET (short to GND) on OUT1
2OCP_L1R0b1b indicates that an over current has been detected on the low-side FET (short to VM) on OUT1
1OCP_H2R0b1b indicates that an over current has been detected on the high-side FET (short to GND) on OUT2
0OCP_L2R0b1b indicates that an over current has been detected on the low-side FET (short to VM) on OUT2

8.1.4 STATUS2 Register (Address = 03h) [reset = 80h]

Return to the User Register table.

BitFieldTypeResetDescription
7DRVOFF_STATR1b

This bit shows the status of the DRVOFF pin. 1b implies the pin status is high.

6, 5N/AR0bNot available
4ACTIVER0b1b indicates that the device is in the ACTIVE state (Copy of bit4 in STATUS1)
3, 2, 1N/AR0bNot available
0OLP_CMPR0bThis bit is the output of the off-state diagnostics (OLP) comparator.

8.1.5 COMMAND Register (Address = 08h) [reset = 09h]

Return to the User Register table.

BitFieldTypeResetDescription
7CLR_FLTR/W0bClear Fault command - Write 1b to clear all faults reported in the fault registers and de-assert the nFAULT pin
6-5N/AR0bNot available
4-3SPI_IN_LOCKR/W01b

Write 10b to unlock the SPI_IN register

Write 01b or 00b or 11b to lock the SPI_IN register

SPI_IN register is locked by default.

2N/AR0b

Not available

1-0REG_LOCKR/W01b

Write 10b to lock the CONFIG registers

Write 01b or 00b or 11b to unlock the CONFIG registers

CONFIG registers are unlocked by default.

8.1.6 SPI_IN Register (Address = 09h) [reset = 0Ch]

Return to the User Register table.

BitFieldTypeResetDescription
7-4N/AR0bNot available
3S_DRVOFFR/W1bRegister bit equivalent of DRVOFF pin when SPI_IN is unlocked. Refer Register Pin control section.
2 RESERVED R 0b Reserved
1S_EN_IN1R/W0bRegister bit equivalent of EN/IN1 pin when SPI_IN is unlocked. Refer Register Pin control section
0S_PH_IN2R/W0bRegister bit equivalent of PH/IN2 pin when SPI_IN is unlocked. Refer Register Pin control section

8.1.7 CONFIG1 Register (Address = 0Ah) [reset = 10h]

Return to the User Register table.

BitFieldTypeResetDescription
7EN_OLAR/W0bWrite 1b to enable open load detection in the active state.
6-5VMOV_SELR/W0bDetermines the thresholds for the VM over voltage diagnostics

00b = VM > 35 V

01b = VM > 28 V

10b = VM > 18 V

11b = VMOV disabled

4SSC_DISR/W1b0b: Enables the spread spectrum clocking feature
3OCP_RETRYR/W0bWrite 1b to configure fault reaction to retry setting on the detection of over current, else the fault reaction is latched
2TSD_RETRYR/W0bWrite 1b to configure fault reaction to retry setting on the detection of over temperature, else the fault reaction is latched
1VMOV_RETRYR/W0bWrite 1b to configure fault reaction to retry setting on the detection of VMOV, else the fault reaction is latched.
Note: For the SPI (P) variant, this bit also controls the fault reaction for a VM under voltage detection.
0OLA_RETRYR/W0bWrite 1b to configure fault reaction to retry setting on the detection of open load during active, else the fault reaction is latched.

8.1.8 CONFIG2 Register (Address = 0Bh) [reset = 00h]

Return to the User Register table.

BitFieldTypeResetDescription
7PWM_EXTENDR/W0bWrite 1b to access additional Hi-Z (coast) states in the PWM mode - refer PWM EXTEND table
6-5S_DIAGR/W0bLoad type indication - refer to DIAG table
4N/AR0bNot available
3 OLA_FLTR R/W 0b Selects OLA filter count. 0b = 16 count, 1b = 1024 count.
2-0S_ITRIPR/W0bITRIP level configuration - refer ITRIP table

8.1.9 CONFIG3 Register (Address = 0Ch) [reset = 40h]

Return to the User Register table.

BitFieldTypeResetDescription
7-6TOFFR/W1bTOFF time used for ITRIP current regulation

00b = 20 µsec

01b = 30 µsec

10b = 40 µsec

11b = 50 µsec

5N/AR0bNot available
4-2S_SRR/W0bSlew Rate configuration - refer to Section 7.3.3.1
1-0S_MODER/W0bDevice mode configuration - refer MODE table

8.1.10 CONFIG4 Register (Address = 0Dh) [reset = 04h]

Return to the User Register table.

BitFieldTypeResetDescription
7-6TOCP_SELR/W0bFilter time for over current detection configuration

00b = 6 µsec

01b = 3 µsec

10b = 1.5 µsec

11b = Minimum (~0.2 µsec)

5N/AR0bNot available
4-3OCP_SELR/W0bThreshold for over current detection configuration

00b = 100% setting

01b, 11b = 50% setting

10b = 75% setting

2DRVOFF_SELR/W1bDRVOFF pin - register logic combination, when SPI_IN is unlocked

0b = OR

1b = AND

1EN_IN1_SELR/W0bEN/IN1 pin - register logic combination, when SPI_IN is unlocked

0b = OR

1b = AND

0PH_IN2_SELR/W0bPH/IN2 pin - register logic combination, when SPI_IN is unlocked

0b = OR

1b = AND