JAJSFH4B November 2017 – July 2018 DRV8304
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
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The OCP control register is shown in Figure 43 and described in Table 17.
Register access type: Read/Write
10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRETRY | DEAD_TIME | OCP_MODE | OCP_ACT | Reserved | VDS_LVL | |||||
R/W-0b | R/W-01b | R/W-01b | R/W-0b | R/W-00b | R/W-101b |
Bit | Field | Type | Default | Description |
---|---|---|---|---|
10 | TRETRY | R/W | 0b |
0b = VDS_OCP and SEN_OCP retry time is 4 ms 1b = VDS_OCP and SEN_OCP retry time is 50 µs |
9-8 | DEAD_TIME | R/W | 01b |
00b = 50-ns dead time 01b = 100-ns dead time 10b = 200-ns dead time 11b = 400-ns dead time |
7-6 | OCP_MODE | R/W | 01b |
00b = Overcurrent causes a latched fault 01b = Overcurrent causes an automatic retrying fault 10b = Overcurrent is report only but no action is taken 11b = Overcurrent is not reported and no action is taken |
5 | OCP_ACT | R/W | 0b |
0b = All three half-bridges are shutdown in response to VDS_OCP and SEN_OCP 1b = Associated half-bridge is shutdown in response to VDS_OCP and SEN_OCP |
4-3 | Reserved | R/W | 00b |
Reserved |
2-0 | VDS_LVL | R/W | 101b |
000b = 0.15 V 001b = 0.24 V 010b = 0.40V 011b = 0.51 V 100b = 0.60 V 101b = 0.90 V 110b = 1.8 V 111b = VDS Disabled |