SLVSBA5D October   2012  – April 2016 DRV8313

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Stage
      2. 7.3.2 Bridge Control
      3. 7.3.3 Charge Pump
      4. 7.3.4 Comparator
      5. 7.3.5 Protection Circuits
        1. 7.3.5.1 Undervoltage Lockout (UVLO)
        2. 7.3.5.2 Thermal Shutdown (TSD)
        3. 7.3.5.3 Overcurrent Protection (OCP)
    4. 7.4 Device Functional Modes
      1. 7.4.1 nRESET and nSLEEP Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Three-Phase Brushless-DC Motor Control
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Motor Voltage
          2. 8.2.1.2.2 Motor Commutation
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Three-Phase Brushless-DC Motor Control With Current Monitor
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Trip Current
          2. 8.2.2.2.2 Sense Resistor
      3. 8.2.3 Brushed-DC and Solenoid Load
        1. 8.2.3.1 Design Requirements
          1. 8.2.3.1.1 Detailed Design Procedure
      4. 8.2.4 Three Solenoid Loads
        1. 8.2.4.1 Design Requirements
          1. 8.2.4.1.1 Detailed Design Procedure
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Heatsinking
    4. 10.4 Power Dissipation
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

The bulk capacitor should be placed to minimize the distance of the high-current path through the motor driver device. The connecting metal trace widths should be as wide as possible, and numerous vias should be used when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high current.

Small-value capacitors should be ceramic, and placed closely to device pins.

The high-current device outputs should use wide metal traces.

The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias helps dissipate the I2 × rDS(on) heat that is generated in the device.

In Figure 19 and Figure 20, the uncommitted comparator is not used. Because this is the case, the COMPP, COMPN, and COMPO pins are tied to GND.

10.2 Layout Example

DRV8313 layout2.gif Figure 19. Recommended Layout Example For HTSSOP PWP Package
DRV8313 layout3.gif Figure 20. Recommended Layout Example For QFN RHH Package

10.3 Thermal Considerations

The DRV8313 has thermal shutdown (TSD) as previously described. A die temperature in excess of 150°C (minimally) disables the device until the temperature drops to a safe level.

Any tendency of the device to enter thermal shutdown is an indication of excessive power dissipation, insufficient heatsinking, or too high an ambient temperature.

10.3.1 Heatsinking

The PowerPAD package uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, add a number of vias to connect the thermal pad to the ground plane to accomplish this. On PCBs without internal planes, add copper area on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, use thermal vias to transfer the heat between the top and bottom layers.

For details about how to design the PCB, see PowerPAD Thermally Enhanced Package (SLMA002) and PowerPAD Made Easy (SLMA004), which are available at www.ti.com.

In general, providing more copper area allows the dissipation of more power.

10.4 Power Dissipation

The power dissipated in the output FET resistance, or rDS(on) dominates power dissipation in the DRV8313. A rough estimate of average power dissipation of each half-H-bridge when running a static load is:

Equation 2. DRV8313 Eq01-P_SLVSBA5.gif

where

  • P is the power dissipation of one H-bridge,
  • rDS(on) is the resistance of each FET, and
  • IOUT is equal to the average current drawn by the load.

At start-up and fault conditions, this current is much higher than normal running current; remember to take these peak currents and their duration into consideration.

The total device dissipation is the power dissipated in each of the three half-H-bridges added together.

The maximum amount of power that the device can dissipate depends on ambient temperature and heatsinking.

Note that rDS(on) increases with temperature, so as the device heats, the power dissipation increases. Take this into consideration when sizing the heatsink.