SLVSET1 August 2018 DRV8873
PRODUCTION DATA.
IC3 control is shown in Figure 34 and described in Table 26.
Read/Write
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLR_FLT | LOCK | OUT1_DIS | OUT2_DIS | EN_IN1 | PH_IN2 | ||
R/W-0b | R/W-100b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | CLR_FLT | R/W | 0b |
Write a 1b to this bit to clear the fault bits. This bit is automatically reset after a write. |
6-4 | LOCK | R/W | 100b |
Write 011b to this register to lock all register settings in the IC1 control register except to these bits and address 0x04, bit 7 (CLR_FLT)
|
3 | OUT1_DIS | R/W | 0b |
Enabled only in the Independent PWM mode 0b = Half bridge 1 enabled 1b = Half bridge 1 disabled (Hi-Z) |
2 | OUT2_DIS | R/W | 0b |
Enabled only in the Independent PWM mode 0b = Half bridge 2 enabled 1b = Half bridge 2 disabled (Hi-Z) |
1 | EN_IN1 | R/W | 0b |
EN/IN1 bit to control the outputs through SPI (when SPI_IN = 1b) |
0 | PH_IN2 | R/W | 0b |
PH/IN2 bit to control the outputs through SPI (when SPI_IN = 1b) |