JAJSGJ0D October 2014 – February 2022 DS90UH948-Q1
PRODUCTION DATA
In the HDCP repeater application, this document refers to the DS90UH947-Q1 as the HDCP transmitter (TX), and refers to the DS90UH948-Q1 as the HDCP receiver (RX). #SNLS44049946 shows the maximum configuration supported for HDCP repeater implementations. Two levels of HDCP repeaters are supported with a maximum of three HDCP Transmitters per HDCP receiver.
In a repeater application, the I2C interface at each TX and RX is configured to transparently pass I2C communications upstream or downstream to any I2C device within the system. This includes a mechanism for assigning alternate IDs (Target Aliases) to downstream devices in the case of duplicate addresses.
To support HDCP repeater operation, the RX includes the ability to control the downstream authentication process, assemble the KSV list for downstream HDCP receivers, and pass the KSV list to the upstream HDCP transmitter. An I2C Controller within the RX communicates with the I2C Target within the TX. The TX handles authenticating with a downstream HDCP Receiver and makes status available through the I2C interface. The RX monitors the transmit port status for each TX and reads downstream KSV and KSV list values from the TX.
In addition to the I2C interface used to control the authentication process, the HDCP repeater implementation includes two other interfaces. The FPD-Link LVDS interface outputs the unencrypted video data. In addition to providing the video data, the LVDS interface communicates control information and packetized audio data. All audio and video data is decrypted at the output of the HDCP receiver and is re-encrypted by the HDCP transmitter. #SNLS44049954 provides more detailed block diagram of a 1:2 HDCP repeater configuration.
If the repeater node includes a local output to a display, white-balancing and Hi-FRC dithering functions must not be used as they will block encrypted I2S audio and HDCP authentication.