JAJSBE6D May   2010  – December 2016 DS92LV0421 , DS92LV0422

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
  4. 改訂履歴
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Serializer DC
    6. 6.6  Electrical Characteristics: Deserializer DC
    7. 6.7  Electrical Characteristics: DC and AC Serial Control Bus
    8. 6.8  Timing Requirements: Serial Control Bus
    9. 6.9  Switching Characteristics: Serializer
    10. 6.10 Switching Characteristics: Deserializer
    11. 6.11 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Parallel LVDS Data Transfer (Color Bit Mapping Select)
      2. 7.3.2 Serial Data Transfer
      3. 7.3.3 Video Control Signal Filter
      4. 7.3.4 Serializer Functional Description
        1. 7.3.4.1 Signal Quality Enhancers
          1. 7.3.4.1.1 Serializer VOD Select (VODSEL)
          2. 7.3.4.1.2 Serializer De-Emphasis (DE-EMPH)
        2. 7.3.4.2 EMI Reduction Features
          1. 7.3.4.2.1 Data Randomization and Scrambling
          2. 7.3.4.2.2 Serializer Spread Spectrum Compatibility
        3. 7.3.4.3 Power-Saving Features
          1. 7.3.4.3.1 Serializer Power-Down Feature (PDB)
          2. 7.3.4.3.2 Serializer Stop Clock Feature
          3. 7.3.4.3.3 Serializer 1.8-V or 3.3-V VDDIO Operation
      5. 7.3.5 Deserializer Functional Description
        1. 7.3.5.1 Signal Quality Enhancers
          1. 7.3.5.1.1 Deserializer Input Equalizer Gain (EQ)
        2. 7.3.5.2 EMI Reduction Features
          1. 7.3.5.2.1 Deserializer VOD Select (VODSEL)
          2. 7.3.5.2.2 Deserializer Common-Mode Filter Pin (CMF) (Optional)
          3. 7.3.5.2.3 Deserializer SSCG Generation (Optional)
          4. 7.3.5.2.4 Power-Saving Features
            1. 7.3.5.2.4.1 Deserializer Power-Down Feature (PDB)
            2. 7.3.5.2.4.2 Deserializer Stop Stream SLEEP Feature
            3. 7.3.5.2.4.3 Deserializer 1.8-V or 3.3-V VDDIO Operation
        3. 7.3.5.3 Deserializer Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN), and Output State Select (OSS_SEL)
        4. 7.3.5.4 Deserializer Oscillator Output (Optional)
      6. 7.3.6 Built-In Self Test (BIST)
        1. 7.3.6.1 Sample BIST Sequence
        2. 7.3.6.2 BER Calculations
      7. 7.3.7 Optional Serial Bus Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serializer and Deserializer Operating Modes and Reverse Compatibility (CONFIG[1:0])
    5. 7.5 Register Maps
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Display Application
      2. 8.1.2 Live Link Insertion
      3. 8.1.3 Alternate Color or Data Mapping
    2. 8.2 Typical Application
      1. 8.2.1 DS92LV0421 Typical Connection
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DS92LV0422 Typical Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 WQFN (LLP) Stencil Guidelines
      2. 10.1.2 Transmission Media
      3. 10.1.3 LVDS Interconnect Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 開発サポート
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 関連リンク
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 コミュニティ・リソース
    6. 11.6 商標
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 用語集
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • NJK|36
サーマルパッド・メカニカル・データ
発注情報

Layout

Layout Guidelines

Circuit board layout and stack-up for the LVDS serializer and deserializer devices must be designed to provide low-noise power feed to the device. Good layout practice also separates high frequency or high-level inputs and outputs to minimize unwanted stray noise pickup, feedback, and interference. Power system performance may be greatly improved by using thin dielectrics (2 to 4 mils) for power or ground sandwiches. This arrangement provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at high frequencies and makes the value and placement of external bypass capacitors less critical. External bypass capacitors must include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2-µF to 10-µF range. Voltage rating of the tantalum capacitors must be at least 5x the power supply voltage being used.

Surface-mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per supply pin, place the smaller value closer to the pin. A large bulk capacitor is recommended at the point of power entry. This is typically in the 50-µF to 100-µF range and smooths low frequency switching noise. TI recommends connecting power and ground pins directly to the power and ground planes with bypass capacitors connected to the plane, with vias on both ends of the capacitor. Connecting power or ground pins to an external bypass capacitor increases the inductance of the path.

A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20 to 30 MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing the impedance at high frequency.

Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as PLLs.

Use at least a four-layer board with a power and ground plane. Place LVCMOS signals away from the CML lines to prevent coupling from the LVCMOS lines to the CML lines. Closely-coupled differential lines of 100 Ω are typically recommended for LVDS interconnects. The closely coupled lines help to ensure that coupled noise appears as common mode and thus is rejected by the receivers. The tightly coupled lines also radiate less.

WQFN (LLP) Stencil Guidelines

Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste deposition. Inspection of the stencil prior to placement of the LLP (WQFN) package is highly recommended to improve board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown in Figure 42 and Figure 43.

DS92LV0421 DS92LV0422 LLP_stencil_nopullback_explanation_diagram_snls302.png Figure 42. No Pullback LLP, Single Row Reference Diagram

Table 18. No Pullback LLP Stencil Aperture Summary for DS92LV0421 and DS92LV0422

DEVICE PIN COUNT MKT DWG PCB I/O PAD SIZE (mm) PCB PITCH (mm) PCB DAP SIZE (mm) STENCIL I/O APERTURE (mm) STENCIL DAP APERTURE (mm) NUMBER OF DAP APERTURE OPENINGS GAP BETWEEN DAP APERTURE (Dim A mm)
DS92LV0421 36 SQA36A 0.25 × 0.6 0.5 4.6 x 4.6 0.25 × 0.7 1.0 × 1.0 16 0.2
DS92LV0422 48 SQA48A 0.25 × 0.6 0.5 5.1 × 5.1 0.25 × 0.7 1.1 × 1.1 16 0.2
DS92LV0421 DS92LV0422 sample_layout_DAP_snls302.png Figure 43. 48-Pin WQFN Stencil Example of Via and Opening Placement

Information on the WQFN style package is provided in Leadless Leadframe Package (LLP) Application Report (SNOA401).

Transmission Media

The serializer and deserializer chipset is intended to be used in a point-to-point configuration through a PCB trace or through twisted pair cable. The serializer and deserializer provide internal terminations for a clean signaling environment. The interconnect for LVDS must present a differential impedance of 100 Ω. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Shielded or un-shielded cables may be used depending upon the noise environment and application requirements.

LVDS Interconnect Guidelines

See AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008) and AN-905 Transmission Line RAPIDESIGNER Operation and Applications Guide (SNLA035) for full details.

  • Use 100-Ω coupled differential pairs
  • Use the S, 2S, 3S rule in spacings
    • S = space between the pair
    • 2S = space between pairs
    • 3S = space to LVCMOS signal
  • Minimize the number of vias
  • Use differential connectors when operating above 500-Mbps line speed
  • Maintain balance of the traces
  • Minimize skew within the pair
  • Terminate as close to the Tx outputs and Rx inputs as possible

Additional general guidance can be found in the LVDS Owner's Manual, available in PDF format from the TI website at: www.ti.com/lvds.

Layout Example

The following PCB layout examples are derived from the layout design of the LV04EVK01 Evaluation Module. These graphics and additional layout description are used to demonstrate both proper routing and proper solder techniques when designing in the serializer and deserializer pair.

DS92LV0421 DS92LV0422 ds92lv0421_layout.png Figure 44. DS92LV0421 Serializer Example Layout
DS92LV0421 DS92LV0422 ds92lv0422_layout.png Figure 45. DS92LV0422 Deserializer Example Layout