JAJSES7A
February 2018 – April 2018
ESD204
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
代表的なアプリケーションの回路図
4
改訂履歴
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings -JEDEC Specifications
6.3
ESD Ratings - IEC Specifications
6.4
Recommended Operating Conditions
6.5
Thermal Information
6.6
Electrical Characteristics
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Signal Range
8.2.2.2
Operating Frequency
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Examples
11
デバイスおよびドキュメントのサポート
11.1
ドキュメントの更新通知を受け取る方法
11.2
コミュニティ・リソース
11.3
商標
11.4
静電気放電に関する注意事項
11.5
Glossary
12
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DQA|10
MPSS004C
サーマルパッド・メカニカル・データ
DQA|10
QFND791
発注情報
jajses7a_oa
jajses7a_pm
6.7
Typical Characteristics
Figure 1.
Positive TLP Curve, IO pin to GND (t
p
= 100 ns)
Figure 3.
Surge Curve (t
p
= 8/20 µs), any IO pin to GND
Figure 5.
–8-kV IEC 61000-4-2 Clamping Voltage Waveform, GND pin to IO
Figure 7.
Leakage Current vs Temperature, IO pin to GND at 3.6 V Bias
Figure 9.
Capacitance vs Frequency
Figure 2.
Negative TLP Curve, GND to IO pin (t
p
=100 ns; Plotted as Positive TLP Curve from GND to IO pin)
Figure 4.
8-kV IEC 61000-4-2 Clamping Voltage Waveform, IO pin to GND
Figure 6.
Capacitance vs Bias Voltage
Figure 8.
DC Voltage Sweep I-V Curve, IO pin to GND
Figure 10.
Differential Insertion Loss