There are several memories, digital peripherals, and analog peripherals that can be accessed by both the Master and Control Subsystems. They are grouped into the Shared Resources and the Analog Subsystem.
The Shared Resources include the EPI, IPC registers, MTOC Message RAM, CTOM Message RAM, and eight individually configurable Shared RAM blocks.
The Message RAMs and the Shared RAMs can be accessed by the C28x CPU and DMA and have Parity-Error Checking. The MTOC Message RAM is intended for sending data from the Master Subsystem to the Control Subsystem, having R/W access for the Cortex-M3/µDMA and read-only access for the C28x/DMA. The CTOM Message RAM is intended for sending data from the Control Subsystem to the Master Subsystem, having R/W access for the C28x/DMA and read-only access for the Cortex-M3/µDMA.
The IPC registers provide up to 32 handshaking channels to coordinate transfer of data through the Message RAMs by polling. Four of these channels are also backed up by four interrupts to PIE on the Control Subsystem side, and four interrupts to the NVIC on the Master Subsystem side (to reduce delays associated with polling).
The eight Shared RAM blocks are similar to the Message RAMs, in that the data flow is only one way; however, the direction of the data flow can be individually set for each block to be from Master to Control Subsystem or from Control to Master Subsystem.
See Section 5.10 for more information on shared resources and analog peripherals.