JAJSCQ8D November   2016  – December 2022 ISO1540-Q1 , ISO1541-Q1

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Supply Current Characteristics
    11. 6.11 Timing Requirements
    12. 6.12 Switching Characteristics
    13. 6.13 Insulation Characteristics Curves
    14. 6.14 Typical Characteristics
      1.      Parameter Measurement Information
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
    4. 7.4 Isolator Functional Principle
      1. 7.4.1 Receive Direction (Left Diagram of )
      2. 7.4.2 Transmit Direction (Right Diagram of )
    5. 7.5 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 I2C Bus Overview
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Material
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Isolator Functional Principle

To isolate a bidirectional signal path (SDA or SCL), the ISO1540-Q1 internally splits a bidirectional line into two unidirectional signal lines, each of which is isolated through a single-channel digital isolator. Each channel output is made open-drain to comply with the open-drain technology of I2C. Side 1 of the ISO1540-Q1 connects to a low-capacitance I2C node, while side 2 is designed for connecting to a fully loaded I2C bus with up to 400 pF of capacitance.

GUID-8682B6EA-81DA-4B0F-BE73-53DA559958A8-low.gifFigure 7-3 SDA Channel Design and Voltage Levels at SDA1

At first sight, the arrangement of the internal buffers suggests a closed signal loop that is prone to latch-up. However, this loop is broken by implementing an output buffer (B) whose output low-level is raised by a diode drop to approximately 0.75 V, and the input buffer (C) that consists of a comparator with defined hysteresis. The comparator’s upper and lower input thresholds then distinguish between the proper low-potential of 0.4 V (maximum) driven directly by SDA1 and the buffered output low-level of B.

Figure 7-4 demonstrate the switching behavior of the I2C isolator, ISO1540-Q1, between a controller node at SDA1 and a heavy loaded bus at SDA2.

GUID-AC6E879A-CE45-4FA6-8B06-1C64DFA2D8AF-low.gifFigure 7-4 SDA Channel Timing in Receive and Transmit Directions