JAJSQG0C june   2015  – may 2023 ISO5851

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 概要 (続き)
  7. 6 Pin Configuration and Function
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Characteristics
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Insulation Characteristics Curves
    12. 7.12 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Supply and Active Miller Clamp
      2. 9.3.2 Active Output Pulldown
      3. 9.3.3 Undervoltage Lockout (UVLO) With Ready (RDY) Pin Indication Output
      4. 9.3.4 Fault ( FLT) and Reset ( RST)
      5. 9.3.5 Short Circuit Clamp
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Recommended ISO5851 Application Circuit
        2. 10.2.2.2  FLT and RDY Pin Circuitry
        3. 10.2.2.3  Driving the Control Inputs
        4. 10.2.2.4  Local Shutdown and Reset
        5. 10.2.2.5  Global-Shutdown and Reset
        6. 10.2.2.6  Auto-Reset
        7. 10.2.2.7  DESAT Pin Protection
        8. 10.2.2.8  DESAT Diode and DESAT Threshold
        9. 10.2.2.9  Determining the Maximum Available, Dynamic Output Power, POD-max
        10. 10.2.2.10 Example
        11. 10.2.2.11 Higher Output Current Using an External Current Buffer
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 PCB Material
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 サード・パーティ製品に関する免責事項
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 用語集
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DW|16
サーマルパッド・メカニカル・データ
発注情報

7.10 Switching Characteristics

Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
trOutput signal rise timeCLOAD = 1 nF, see Figure 8-1, Figure 8-2, and Figure 8-3122035ns
tfOutput signal fall time122037ns
tPLH, tPHLPropagation Delay76110ns
tsk-pPulse Skew |tPHL – tPLH|20ns
tsk-ppPart-to-part skew30(1)ns
tGFGlitch filter on IN+, IN–, RST203040ns
tDESAT (10%)DESAT sense to 10% OUT delay300415500ns
tDESAT (GF)DESAT glitch filter delay330ns
tDESAT ( FLT)DESAT sense to FLT-low delaysee Figure 8-320002420ns
tLEBLeading edge blanking timesee Figure 8-1 and Figure 8-2330400500ns
tGF(RSTFLT)Glitch filter on RST for resetting FLT300800ns
CIInput capacitance(2)VI = VCC1 /2 + 0.4 x sin (2πft), f = 1 MHz, VCC1 = 5 V2pF
CMTICommon-mode transient immunityVCM = 1500 V, see Figure 8-4100120kV/μs
(1) Measured at same supply voltage and temperature condition
(2) Measured from input pin to ground.