JAJSGK0C November   2018  – October 2022 ISO7760-Q1 , ISO7761-Q1 , ISO7762-Q1 , ISO7763-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics—5-V Supply
    10. 7.10 Supply Current Characteristics—5-V Supply
    11. 7.11 Electrical Characteristics—3.3-V Supply
    12. 7.12 Supply Current Characteristics—3.3-V Supply
    13. 7.13 Electrical Characteristics—2.5-V Supply
    14. 7.14 Supply Current Characteristics—2.5-V Supply
    15. 7.15 Switching Characteristics—5-V Supply
    16. 7.16 Switching Characteristics—3.3-V Supply
    17. 7.17 Switching Characteristics—2.5-V Supply
    18. 7.18 Insulation Characteristics Curves
    19. 7.19 Typical Characteristics
      1.      Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Electromagnetic Compatibility (EMC) Considerations
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device I/O Schematics
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
        1. 9.2.3.1 Insulation Lifetime
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT
DW-16 DBQ-16
CLR External clearance#SLLSER11001 Shortest terminal-to-terminal distance through air >8 >3.7 mm
CPG External creepage#SLLSER11001 Shortest terminal-to-terminal distance across the package surface >8 >3.7 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >21 >21 μm
CTI Tracking resistance (comparative tracking index) DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A >600 >600 V
Material group According to IEC 60664-1 I I
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 150 VRMS I–IV I–IV
Rated mains voltage ≤ 300 VRMS I–IV I–III
Rated mains voltage ≤ 600 VRMS I–IV n/a
Rated mains voltage ≤ 1000 VRMS I–III n/a
DIN EN IEC 60747-17 (VDE 0884-17)#SLLSER14992
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 2121 566 VPK
VIOWM Maximum working isolation voltage AC voltage; Time dependent dielectric breakdown (TDDB) test; see GUID-14984C4D-6FB0-4C33-B2B4-BFFD68860585.html#T4174073-12 1500 400 VRMS
DC voltage 2121 566 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM , t = 60 s (qualification)
VTEST = 1.2 x VIOTM, t = 1 s (100% production)		 8000 4242 VPK
VIMP

Maximum impulse voltage#GUID-FBD46DFC-CF91-42E6-B38A-03BCA1A91B00

Tested in air, 1.2/50-μs waveform per IEC 62368-1

8000

4000

 VPK
VIOSM Maximum surge isolation voltage#SLLSER14749

Tested in oil (qualification test), 1.2/50-μs waveform per IEC 62368-1

 12800 10000 VPK
qpd Apparent charge#SLLSER12150 Method a, After Input/Output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM, tm = 10 s		 ≤5 ≤5 pC
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM, tm = 10 s		 ≤5 ≤5

Method b: At routine test (100% production) and preconditioning (type test);

Vini = 1.2 x VIOTM, tini = 1 s;

Vpd(m) = 1.875 x VIORM, tm = 1 s (method b1) or

Vpd(m) = Vini, tm = tini (method b2)

 ≤5 ≤5
CIO Barrier capacitance, input to output#SLLSER1481 VIO = 0.4 × sin (2πft), f = 1 MHz ~1.1 ~0.9 pF
RIO Isolation resistance#SLLSER1481 VIO = 500 V, TA = 25°C >1012 >1012 Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C >1011 >1011
VIO = 500 V, TS = 150°C >109 >109
Pollution degree 2 2
Climatic category 55/125/
21		 55/125/
21
UL 1577
VISO Withstanding isolation voltage VTEST = VISO , t = 60 s (qualification),
VTEST = 1.2 × VISO , t = 1 s (100% production)		 5000 3000 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air to determine the surge immunity of the package.
(4) Testing is carried in oil to determine the intrinsic surge immunity of the isolation barrier.
(5) Apparent charge is electrical discharge caused by a partial discharge (pd).
(6) All pins on each side of the barrier tied together creating a two-terminal device.