7.3.1 UVLO

An undervoltage lockout pin is provided to disable the regulator when the input is below the desired operating range. If the UVLO pin is below 1.13 V, the regulator enters a standby mode with the outputs disabled, but with VCC regulator operating. If the UVLO input exceeds 1.23 V, the regulator will resume normal operation. A voltage divider from the input to ground can be used to set a VIN threshold to disable the regulator in brownout conditions or for low input faults.

If a current limit fault exists for more than 256 clock cycles, the regulator will enter a hiccup mode of current limiting and the UVLO pin will be pulled low by an internal switch. This switch turns off when the UVLO pin approaches ground potential allowing the UVLO pin to rise. A capacitor connected to the UVLO pin will delay the return to a normal operating level and thereby set the off-time of the hiccup mode fault protection. An internal 5-µA pullup current pulls the UVLO pin to a high state to ensure normal operation when the VIN UVLO function is not required and the pin is left floating.

7.3.2 Oscillator and Sync Capability

The LM25118-Q1 oscillator frequency is set by a single external resistor connected between the RT pin and the AGND pin. The R_T resistor should be located very close to the device and connected directly to the pins of the IC. To set a desired oscillator frequency (f), the necessary value for the R_T resistor can be calculated from Equation 1:

Equation 1.

The SYNC pin can be used to synchronize the internal oscillator to an external clock. The external clock must be of higher frequency than the free-running frequency set by the R_T resistor. A clock circuit with an open-drain output is the recommended interface from the external clock to the SYNC pin. The clock pulse duration should be greater than 15 ns.

Figure 11. Sync From Multiple Devices

Multiple LM25118-Q1 devices can be synchronized together simply by connecting the SYNC pins together. In this configuration, all of the devices will be synchronized to the highest frequency device. The diagram in Figure 11 shows the SYNC input and output features of the LM25118-Q1. The internal oscillator circuit drives the SYNC pin with a strong pulldown and weak pullup inverter. When the SYNC pin is pulled low, either by the internal oscillator or an external clock, the ramp cycle of the oscillator is terminated and forced 400 ns off-time is initiated before a new oscillator cycle begins. If the SYNC pins of several LM25118-Q1 ICs are connected together, the IC with the highest internal clock frequency will pull all the connected SYNC pins low and terminate the oscillator ramp cycles of the other ICs. The LM25118-Q1 with the highest programmed clock frequency will serve as the master and control the switching frequency of all the devices with lower oscillator frequencies.

Figure 12. Simplified Oscillator and Block Diagram With Sync I/O Circuit

7.3.3 Error Amplifier and PWM Comparator

The internal high gain error amplifier generates an error signal proportional to the difference between the regulated output voltage and an internal precision reference (1.23 V). The output of the error amplifier is connected to the COMP pin. Loop compensation components, typically a type II network shown in Figure 18 are connected between the COMP and FB pins. This network creates a low-frequency pole, a zero, and a noise reducing high-frequency pole. The PWM comparator compares the emulated current sense signal from the RAMP generator to the error amplifier output voltage at the COMP pin. The same error amplifier is used for operation in buck and buck-boost mode.

Figure 13. Composition of Emulated Current Signal

7.3.4 Ramp Generator

The ramp signal of a pulse-width modulator with current mode control is typically derived directly from the buck switch drain current. This switch current corresponds to the positive slope portion of the inductor current signal. Using this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and provides inherent input voltage feed-forward compensation. The disadvantage of using the buck switch current signal for PWM control is the large leading edge spike due to circuit parasitics. The leading edge spike must be filtered or blanked to avoid early termination of the PWM pulse. Also, the current measurement may introduce significant propagation delays. The filtering, blanking time, and propagation delay limit the minimal achievable pulse width. In applications where the input voltage may be relatively large in comparison to the output voltage, controlling a small pulse width is necessary for regulation. The LM25118-Q1 uses a unique ramp generator which does not actually measure the buck switch current but instead creates a signal representing or emulating the inductor current. The emulated ramp provides signal to the PWM comparator that is free of leading edge spikes and measurement or filtering delays. The current reconstruction is comprised of two elements: a sample-and-hold pedestal level and a ramp capacitor that is charged by a controlled current source. See Figure 13 for details.

The sample-and-hold pedestal level is derived from a measurement of the recirculating current through a current sense resistor in series with the recirculating diode of the buck regulator stage. A small value current-sensing resistor is required between the recirculating diode anode and ground. The CS and CSG pins should be Kelvin connected directly to the sense resistor. The voltage level across the sense resistor is sampled and held just prior to the onset of the next conduction interval of the buck switch. The current sensing and sample-and-hold provide the DC level of the reconstructed current signal. The sample and hold of the recirculating diode current is valid for both buck and buck-boost modes. The positive slope inductor current ramp is emulated by an external capacitor connected from the RAMP pin to the AGND and an internal voltage controlled current source. In buck mode, the ramp current source that emulates the inductor current is a function of the VIN and VOUT voltages per Equation 2.

Equation 2.

In buck-boost mode, the ramp current source is a function of the input voltage VIN, per Equation 3.

Equation 3.

Proper selection of the RAMP capacitor (C_RAMP) depends upon the value of the output inductor (L) and the current sense resistor (R_S). For proper current emulation, the sample and hold pedestal value and the ramp amplitude must have the same relative relationship to the actual inductor current. That is:

Equation 4.

where

• g_m is the ramp generator transconductance (5 µA/V)
• A is the current sense amplifier gain (10 V/V)

The ramp capacitor should be located very close to the device and connected directly to the RAMP and AGND pins.

The relationship between the average inductor current and the pedestal value of the sampled inductor current can cause instability in certain operating conditions. This instability is known as sub-harmonic oscillation, which occurs when the inductor ripple current does not return to its initial value by the start of the next switching cycle. Sub-harmonic oscillation is normally characterized by observing alternating wide and narrow pulses at the switch node. Adding a fixed slope voltage ramp (slope compensation) to the current sense signal prevents this oscillation. The 50 µA of offset current provided from the emulated current source adds enough slope compensation to the ramp signal for output voltages less than or equal to 12 V. For higher output voltages, additional slope compensation may be required. In such applications, the ramp capacitor can be decreased from the nominal calculated value to increase the ramp slope compensation.

The pedestal current sample is obtained from the current sense resistor (Rs) connected to the CS and CSG pins. It is sometimes helpful to adjust the internal current sense amplifier gain (A) to a lower value to obtain the higher current limit threshold. Adding a pair of external resistors RG in a series with CS and CSG as shown in Figure 14 reduces the current sense amplifier gain A according to Equation 5.

Equation 5.

7.3.5 Current Limit

In the buck mode the average inductor current is equal to the output current (Iout). In buck-boost mode the average inductor current is approximately equal to:

Equation 6.

Consequently, the inductor current in buck-boost mode is much larger especially when VOUT is large relative to VIN. The LM25118-Q1 provides a current monitoring scheme to protect the circuit from possible overcurrent conditions. When set correctly, the emulated current sense signal is proportional to the buck switch current with a scale factor determined by the current sense resistor. The emulated ramp signal is applied to the current limit comparator. If the peak of the emulated ramp signal exceeds 1.25 V when operating in the buck mode, the PWM cycle is immediately terminated (cycle-by-cycle current limiting). In buck-boost mode the current limit threshold is increased to 2.50 V to allow higher peak inductor current. To further protect the external switches during prolonged overload conditions, an internal counter detects consecutive cycles of current limiting. If the counter detects 256 consecutive current limited PWM cycles, the LM25118-Q1 enters a low power dissipation hiccup mode. In the hiccup mode, the output drivers are disabled, the UVLO pin is momentarily pulled low, and the soft-start capacitor is discharged. The regulator is restarted with a normal soft-start sequence once the UVLO pin charges back to 1.23 V. The hiccup mode off-time can be programmed by an external capacitor connected from UVLO pin to ground. This hiccup cycle will repeat until the output overload condition is removed.

In applications with low output inductance and high input voltage, the switch current may overshoot due to the propagation delay of the current limit comparator and control circuitry. If an overshoot should occur, the sample-and-hold circuit will detect the excess recirculating diode current. If the sample-and-hold pedestal level exceeds the internal current limit threshold, the buck switch will be disabled and will skip PWM cycles until the inductor current has decayed below the current limit threshold. This approach prevents current runaway conditions due to propagation delays or inductor saturation since the inductor current is forced to decay before the buck switch is turned on again.

Figure 14. Current Limit and Ramp Circuit

7.3.6 Maximum Duty Cycle

Each conduction cycle of the buck switch is followed by a forced minimum off-time of 400 ns to allow sufficient time for the recirculating diode current to be sampled. This forced off-time limits the maximum duty cycle of the controller. The actual maximum duty cycle will vary with the operating frequency of Equation 7.

Figure 15. Maximum Duty Cycle vs Frequency

Limiting the maximum duty cycle will limit the maximum boost ratio (VOUT/VIN) while operating in buck-boost mode. For example, from Figure 15, at an operating frequency of 500 kHz, D_MAX is 80%. Using the buck-boost transfer function.

Equation 8.

with

• D = 80%, solving for VOUT results in
• VOUT = 4 × VIN

With a minimum input voltage of 5 V, the maximum possible output voltage is 20 V at f = 500 kHz. The buck-boost step-up ratio can be increased by reducing the operating frequency which increases the maximum duty cycle.

7.3.7 Soft Start

The soft-start feature allows the regulator to gradually reach the initial steady-state operating point, thus reducing start-up stresses and surges. The internal 10-µA soft-start current source gradually charges an external soft-start capacitor connected to the SS pin. The SS pin is connected to the positive input of the internal error amplifier. The error amplifier controls the pulse-width modulator such that the FB pin approximately equals the SS pin as the SS capacitor is charged. Once the SS pin voltage exceeds the internal 1.23-V reference voltage, the error amp is controlled by the reference instead of the SS pin. The SS pin voltage is clamped by an internal amplifier at a level of 150 mV above the FB pin voltage. This feature provides a soft-start controlled recovery in the event a severe overload pulls the output voltage (and FB pin) well below normal regulation but doesn’t persist for 256 clock cycles.

Various sequencing and tracking schemes can be implemented using external circuits that limit or clamp the voltage level of the SS pin. The SS pin acts as a noninverting input to the error amplifier anytime SS voltage is less than the 1.23-V reference. In the event a fault is detected (overtemperature, VCC undervoltage, hiccup current limit), the soft-start capacitor will be discharged. When the fault condition is no longer present, a new soft-start sequence will begin.

7.3.8 HO Output

The LM25118-Q1 contains a high-side, high-current gate driver and associated high voltage level shift. This gate driver circuit works in conjunction with an internal diode and an external bootstrap capacitor. A 0.1-µF ceramic capacitor, connected with short traces between the HB pin and HS pin is recommended for most circuit configurations. The size of the bootstrap capacitor depends on the gate charge of the external FET. During the off-time of the buck switch, the HS pin voltage is approximately –0.5 V and the bootstrap capacitor is charged from VCC through the internal bootstrap diode. When operating with a high PWM duty cycle, the buck switch will be forced off each cycle for 400 ns to ensure that the bootstrap capacitor is recharged.

7.3.9 Thermal Protection

Internal Thermal Shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low power reset state, disabling the output driver and the bias regulator. This protection is provided to prevent catastrophic failures from accidental device overheating.

7.4.1 Buck Mode Operation: VIN > VOUT

The LM25118-Q1 buck-boost regulator operates as a conventional buck regulator with emulated current mode control while VIN is greater than VOUT and the buck mode duty cycle is less than 75%. In buck mode, the LO gate drive output to the boost switch remains low.

7.4.2 Buck-Boost Mode Operation: VIN ≊ VOUT

When VIN decreases relative to VOUT, the duty cycle of the buck switch will increase to maintain regulation. Once the duty cycle reaches 75%, the boost switch starts to operate with a very small duty cycle. As VIN is further decreased, the boost switch duty cycle increases until it is the same as the buck switch. As VIN is further decreased below VOUT, the buck and boost switch operate together with the same duty cycle and the regulator is in full buck-boost mode. This feature allows the regulator to transition smoothly from buck to buck-boost mode. Note that the regulator can be designed to operate with VIN less than 4 V, but VIN must be at least 5 V during start-up. Figure 16 shows a timing illustration of the gradual transition from buck to buck-boost mode when the input voltage ramps downward over a few switching cycles.

Figure 16. Buck (HO) and Boost (LO) Switch Duty Cycle vs. Time,
Illustrating Gradual Mode Change With Decreasing Input Voltage

7.4.3 High Voltage Start-Up Regulator

The LM25118-Q1 contains a dual-mode, high voltage linear regulator that provides the VCC bias supply for the PWM controller and the MOSFET gate driver. The VIN input pin can be connected directly to input voltages as high as 42 V. For input voltages below 10 V, an internal low dropout switch connects VCC directly to VIN. In this supply range, VCC is approximately equal to VIN. For VIN voltages greater than 10 V, the low dropout switch is disabled and the VCC regulator is enabled to maintain VCC at approximately 7 V. A wide operating range of 4 V to 42 V (with a startup requirement of at least 5 V) is achieved through the use of this dual-mode regulator.

The output of the VCC regulator is current limited to 35 mA, typical. Upon power up, the regulator sources current into the capacitor connected to the VCC pin. When the voltage at the VCC pin exceeds the VCC under-voltage threshold of 3.7 V and the UVLO input pin voltage is greater than 1.23 V, the gate driver outputs are enabled and a soft-start sequence begins. The gate driver outputs remain enabled until VCC falls below 3.5 V or the voltage at the UVLO pin falls below 1.13 V.

In many applications, the regulated output voltage or an auxiliary supply voltage can be applied to the VCCX pin to reduce the IC power dissipation. For output voltages between 4 V and 15 V, VOUT can be connected directly to VCCX. When the voltage at the VCCX pin is greater than 3.85 V, the internal VCC regulator is disabled and an internal switch connects VCCX to VCC, reducing the internal power dissipation.

In high voltage applications, take extra care to ensure the VIN pin voltage does not exceed the absolute maximum voltage rating of 45 V. During line or load transients, voltage ringing on the VIN line that exceeds the absolute maximum rating can damage the IC. Both careful PCB layout and the use of quality bypass capacitors located close to the VIN and GND pins are essential.

Figure 17. VIN and VCC Sequencing

7.4.4 Enable

The LM25118-Q1 contains an enable function which provides a very low input current shutdown mode. If the EN pin is pulled below 0.5 V, the regulator enters shutdown mode, drawing less than 10 µA from the VIN pin. Raising the EN input above 3 V returns the regulator to normal operation. The EN pin can be tied directly to the VIN pin if this function is not needed. It must not be left floating. A 1-MΩ pullup resistor to VIN can be used to interface with an open-collector or open-drain control signal.