JAJSCZ3A March   2017  – February 2018 LM25141-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  High Voltage Start-Up Regulator
      2. 8.3.2  VCC Regulator
      3. 8.3.3  Oscillator
      4. 8.3.4  Synchronization
      5. 8.3.5  Frequency Dithering (Spread Spectrum)
      6. 8.3.6  Enable
      7. 8.3.7  Power Good
      8. 8.3.8  Output Voltage
        1. 8.3.8.1 Minimum Output Voltage Adjustment
      9. 8.3.9  Current Sense
      10. 8.3.10 DCR Current Sensing
      11. 8.3.11 Error Amplifier and PWM Comparator
      12. 8.3.12 Slope Compensation
      13. 8.3.13 Hiccup Mode Current Limiting
      14. 8.3.14 Standby Mode
      15. 8.3.15 Soft Start
      16. 8.3.16 Diode Emulation
      17. 8.3.17 High- and Low-Side Drivers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Inductor Calculation
        3. 9.2.2.3 Current Sense Resistor
        4. 9.2.2.4 Output Capacitor
        5. 9.2.2.5 Input Filter
          1. 9.2.2.5.1 EMI Filter Design
          2. 9.2.2.5.2 MOSFET Selection
          3. 9.2.2.5.3 Driver Slew Rate Control
          4. 9.2.2.5.4 Frequency Dithering
        6. 9.2.2.6 Control Loop
          1. 9.2.2.6.1 Feedback Compensator
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Layout Procedure
    2. 11.2 Layout Examples
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
        1. 12.2.1.1 PCBレイアウトについてのリソース
        2. 12.2.1.2 熱設計についてのリソース
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.8.1 Minimum Output Voltage Adjustment

There are two limitations to the minimum output voltage adjustment range: the LM25141-Q1 voltage reference of 1.2 V and the minimum switch node pulse width, tSW.

The minimum controllable on-time at the switch node (tSW) limits the voltage conversion ratio (VOUT/VIN). For fixed-frequency PWM operation, the voltage conversion ratio should meet the condition in Equation 8:

Equation 8. LM25141-Q1 equation_07_snvsaj6.gif

where

  • tSW is 70 ns (typical)
  • Fsw is the switching frequency

If the desired voltage conversion ratio does not meet the above condition, the controller transitions from fixed frequency operation into a pulse skipping mode to maintain regulation of the output voltage.

For example, if the desired output voltage is 3.3 V with a VIN of 20 V and operating at 2.2 MHz, the voltage conversion ratio test is satisfied:

Equation 9. LM25141-Q1 equation_08_snvsaj6.gif
0.165 > 0.154

For wide VIN applications and lower output voltages, an alternative is to use the LM25141-Q1 with a 440-kHz oscillator frequency. Operating at 440 kHz, the limitation of the minimum tSW time is less significant. For example, if a 1.8-V output is required with a VIN of 42 V:

Equation 10. LM25141-Q1 equation_09_SNVSAP9.gif
0.04286 > 0.0308