7.3.3.1 Fault Operation

Upon entering a fault condition, the LM3556 sets the appropriate flag in the Flags Register (0x0B), placing the part into standby by clearing and locking the Torch Enable bit (TEN), Pre-Charge bit, and Mode bits (M1, M0) in the Enable Register (0x0A), until the Flags Register (0x0B) is read back via I²C.

7.3.3.2 Flash Time-Out

The Flash time-out period sets the amount of time that the flash current is being sourced from the current source (LED). The LM3556 has 8 time-out levels ranging 100 ms to 800 ms in 100-ms steps. The flash time-out period is controlled in the Flash Features Register (0x08). Flash time-out only applies to the Flash Mode operation. The mode bits are cleared upon a flash time-out.

7.3.3.3 Overvoltage Protection (OVP)

The output voltage is limited to typically 5 V (see V_OVP in Electrical Characteristics. In situations such as an open LED, the LM3556 device raises the output voltage in order to keep the LED current at its target value. When V_OUT reaches 5 V (typical), the overvoltage comparator trips and turns off the internal NFET. When V_OUT falls below the V_OVP off threshold, the LM3556 begins switching again. The mode bits in the Enable Register (0x0A) are not cleared upon an OVP.

7.3.3.4 Current Limit

The LM3556 features selectable inductor-current limits that are programmable through the Flash Features Register (0x08) of the I²C-compatible interface. When the inductor-current limit is reached, the LM3556 terminates the charging phase of the switching cycle.

Because the current limit is sensed in the NMOS switch, there is no mechanism to limit the current when the device operates in Pass Mode. In Boost Mode or Pass Mode, if V_OUT falls below 2.3 V, the device stops switching, and the PFET operates as a current source limiting the current to 200 mA. This prevents damage to the LM3556 and excessive current draw from the battery during output short-circuit conditions. The mode bits in the Enable Register (0x0A) are not cleared upon a current limit event.

Pulling additional current from the V_OUT node during normal operation is not recommended.

7.3.3.5 NTC Thermistor Input (TEMP)

The TEMP pin serves as a threshold detector for negative temperature coefficient (NTC) thermistors. It interrupts the LED current when the voltage at TEMP goes below the programmed threshold. The NTC threshold voltage is adjustable from 200 mV to 900 mV in 100-mV steps. The NTC current is adjustable from 25 µA to 100 µA in 25-µA steps. When an overtemperature event is detected, the LM3556 can be set to force the LED current from Flash Mode into Torch Mode or into shutdown. These settings are adjusted via the NTC Settings Register (0x02), and the NTC detection circuitry can be enabled or disabled via the Enable Register (0x0A). If enabled, the NTC block turns on and off during the start and stop of a flash, torch, or indicator event. The NTC mode of operation is set by adjusting the NTC Mode bit in the Configuration Register (0x07). See NTC Settings Register (0x02) for more details. The mode bits in the Enable Register (0x0A) are cleared upon an NTC event.

7.3.3.6 Undervoltage Lockout (UVLO)

The LM3556 has an internal comparator that monitors the voltage at IN and forces the LM3556 into shutdown if the input voltage drops to 2.8 V. If the UVLO monitor threshold is tripped, the UVLO flag bit is set in the Flags Register (0x0B). If the input voltage rises above 2.8 V, the device is available for operation until there is an I²C read command initiated for the Flags Register (0x0B). Upon a read, the Flags Register is cleared, and normal operation can resume. This feature can be disabled by writing a '0' to the UVLO EN bit in the Input Voltage Flash Monitor (IVFM) Mode Register (0x01). The mode bits in the Enable Register (0x0A) are cleared upon a UVLO event.

7.3.3.7 Thermal Shutdown (T_SD)

When the LM3556 device’s die temperature reaches 150°C, the boost converter shuts down, and the NFET and PFET turn off, as does the current source (LED). When the thermal shutdown threshold is tripped, a '1' gets written to the corresponding bit of the Flags Register (0x0B) (T_SD bit), and the device goes into standby. The LM3556 can only restart after the Flags Register (0x0B) is read, clearing the fault flag. Upon restart, if the die temperature is still above 150°C, the device resets the fault flag and re-enters standby. The mode bits in the Enable Register (0x0A) are cleared upon a T_SD.

7.3.3.8 LED and/or V_OUT Fault

The LED fault flag in the Flags Register (0x0B) reads back a '1' if the part is active in Flash Mode or Torch Mode, and the LED output or the V_OUT node experiences a short condition. The LM3556 determines an LED open condition if the OVP threshold is crossed at the OUT pin while the device is in Flash or Torch Mode. An LED short condition is determined if the voltage at LED goes below 500 mV (typical) while the device is in either Torch or Flash Mode. There is a delay of 256-μs deglitch time before the LED flag is valid, and 2.048 ms before the V_OUT flag is valid. This delay is the time between when the flash or torch current is triggered and when the LED voltage and the output voltage are sampled. The LED flag can only be reset to '0' by removing power to the LM3556, or by reading back the Flags Register (0x0B). The mode bits in the Enable Register (0x0A) are cleared upon an LED and/or V_OUT fault.

Table 1. I²C Commands and the State of the Mode Bits

7.5.1.1 Data Validity

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when SCL is LOW.

Figure 29. Data Validity Diagram

A pullup resistor between the controller's VIO line and SDA must be greater than [(VIO – V_OL) / 3mA] to meet the V_OL requirement on SDA. Using a larger pullup resistor results in lower switching current with slower edges, while using a smaller pullup results in higher switching currents with faster edges.

7.5.1.2 Start and Stop Conditions

START and STOP conditions classify the beginning and the end of the I²C session. A START condition is defined as the SDA signal transitioning from HIGH to LOW while SCL line is HIGH. A STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The I²C master always generates START and STOP conditions. The I²C bus is considered to be busy after a START condition and free after a STOP condition. During data transmission, the I²C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise.

Figure 30. Start and Stop Conditions

7.5.1.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LM3556 pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The LM3556 generates an acknowledge after each byte is received. There is no acknowledge created after data is read from the LM3556.

After the START condition, the I²C master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W). The LM3556 7-bit address is 0x63. For the eighth bit, a '0' indicates a WRITE and a '1' indicates a READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register.

W = Write (SDA = '0')
R = Read (SDA = '1')
Ack = Acknowledge (SDA Pulled Down By Either Master Or Slave)
ID= Chip Address, 63h For LM3556

Figure 31. Write Cycle

7.5.1.4 I²C-Compatible Chip Address

The device address for the LM3556 is 1100011 (63). After the START condition, the I²C-compatible master sends the 7-bit address followed by an eighth read or write bit (R/W). R/W = 0 indicates a WRITE and R/W = 1 indicates a READ. The second byte following the device address selects the register address to which the data will be written. The third byte contains the data for the selected register.

Figure 32. I²C-Compatible Device Address

7.5.1.5 Transferring Data

Every byte on the SDA line must be eight bits long, with the most significant bit (MSB) transferred first. Each byte of data must be followed by an acknowledge bit (ACK). The acknowledge related clock pulse (9th clock pulse) is generated by the master. The master releases SDA (HIGH) during the 9th clock pulse. The LM3556 pulls down SDA during the 9th clock pulse, signifying an acknowledge. An acknowledge is generated after each byte has been received.

7.6.1.1 Silicon Revision and Filter Time Register (0x00)

7.6.1.2 Input Voltage Flash Monitor (IVFM) Mode Register (0x01)

Figure 33. Stop and Hold Mode

Figure 34. Adjust Down-Only Mode

Figure 35. Adjust Up and Down Mode

7.6.1.3 NTC Settings Register (0x02)

Figure 36. NTC Control Block

The TEMP node is connected to an NTC resistor as shown in Figure 36 above. A constant current source from the input is connected to this node. Any change in the voltage because of a change in the resistance of the NTC resistor is compared to a set V_TRIP. The trip thresholds are selected by Bits[4:2] of the NTC Register. The output of the Control Logic upon an NTC trip is selected through Bit[5].

7.6.1.4 Indicator Ramp Time Indicator (0x03)

7.6.1.5 Indicator Blinking Register (0x04)

7.6.1.6 Indicator Period Count Register (0x05)

Figure 37. Indicator Usage

1. Number of periods (t_PERIOD = t_R + t_F + t_PULSE × 2)
2. Active Time (t_ACTIVE = t_PERIOD × N_PERIOD)
3. Blank Time (t_BLANK = t_ACTIVE × N_BLANK)

Figure 38. Single Pulse With Dead Time

Figure 39. Multiple Pulse With Dead Time

7.6.1.7 Torch Ramp Time Register (0x06)

7.6.1.8 Configuration Register (0x07)

7.6.1.9 Flash Features Register (0x08)

7.6.1.10 Current Control Register (0x09)

7.6.1.11 Enable Register (0x0A)

7.6.1.11.2 Control Logic Delays

Figure 40. Control Logic Delays

Table 13. Control Logic Delay Timing

DELAY	EXPLANATION	TIME
ta	Time for the LED current to start ramping up after an I2C Write command.	554 µs
tb	Time for the LED current to start ramping down after an I2C Stop command.	32 µs
tc	Time for the LED current to start ramping up after the STROBE pin is raised high.	400 µs
td	Time for the LED current to start ramping down after the STROBE pin is pulled low.	16 µs
te	Time for the LED current to start ramping up after the TORCH pin is raised high.	300 µs
tf	Time for the LED current to start ramping down after the TORCH pin is pulled low.	16 µs
tg	Time for the LED current to start ramping down after the TX pin is pulled high.	3 µs
th	Time for the LED current to start ramping up after the TX pin is pulled low, provide the part has not timed out in Flash Mode.	2 µs

7.6.1.12 Flags Register (0x0B)