JAJSA81F December   2004  – August 2016 LM5025A

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
  4. 改訂履歴
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Voltage Start-Up Regulator
      2. 7.3.2  Line Undervoltage Detector
      3. 7.3.3  PWM Outputs
      4. 7.3.4  Compound Gate Drivers
      5. 7.3.5  PWM Comparator
      6. 7.3.6  Volt Second Clamp
      7. 7.3.7  Current Limit
      8. 7.3.8  Oscillator and Sync Capability
      9. 7.3.9  Feed-Forward Ramp
      10. 7.3.10 Soft Start
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Oscillator
        2. 8.2.2.2 Soft-Start Ramp Time and Hiccup Interval
        3. 8.2.2.3 Feedforward Ramp and Maximum On-Time Clamp
        4. 8.2.2.4 Dead Times
      3. 8.2.3 Application Curves
    3. 8.3 System Example
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Protection
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM5025A PWM controller contains all of the features necessary to implement power converters using the active clamp and reset technique. This section provides design guidance for a typical active clamp forward converter design. An actual application schematic of a 36-V to 78-V input, 3.3-V, 30-A output active clamp forward converter is also provided in Figure 22.

8.2 Typical Application

Figure 14 shows a simplified schematic of an active clamp forward power converter.

Power converters based on the forward topology offer high-efficiency and good power-handling capability in applications up to several hundred Watts. The operation of the transformer in a forward topology does not inherently self-reset each power switching cycle, a mechanism to reset the transformer is required. The active clamp reset mechanism is presently finding extensive use in medium-level power converters in the range of 50 W to 200 W.

The forward converter is derived from the Buck topology family, employing a single modulating power switch. The main difference between the topologies is the forward topology employs a transformer to provide input and output ground isolation and a step-down or step-up function.

Each cycle, the main primary switch turns on and applies the input voltage across the primary winding. The transformer turns the voltage to a lower-level on the secondary side. The clamp capacitor along with the reset switch reverse biases the transformer primary each cycle when the main switch turns off. This reverse voltage resets the transformer. The clamp capacitor voltage is VIN / (1–D).

The secondary rectification employs self-driven synchronous rectification to maintain high-efficiency and ease of drive.

Feedback from the output is processed by an amplifier and reference, generating an error voltage, which is coupled back to the primary side control through an opto-coupler. The LM5025A voltage mode controller pulse width modulates the error signal with a ramp signal derived from the input voltage. Deriving the ramp signal slope from the input voltage provides line feedforward, which improves line transient rejection. The LM5025A also provides a controlled delay necessary for the reset switch.

LM5025A 20107401.gif Figure 14. Simplified Active Clamp Forward Power Converter

8.2.1 Design Requirements

This typical application provides an example of a fully-functional power converter based on the active clamp forward topology in an industry standard half-brick footprint.

The design requirements are:

  • Input: 36 V to 78 V (100-V peak)
  • Output voltage: 3.3 V
  • Output current: 0 A to 30 A
  • Measured efficiency: 90.5% at 30 A, 92.5% at 15 A
  • Frequency of operation: 230 kHz
  • Board size: 2.3 × 2.4 × 0.5 inches
  • Load regulation: 1%
  • Line regulation: 0.1%
  • Line UVLO, hiccup current limit

8.2.2 Detailed Design Procedure

Before the controller design begins, the power stage design must be completed. This section describes the calculations needed to configure the LM5025A controller to meet the power stage design requirements.

8.2.2.1 Oscillator

The desired switching frequency F is set by a resistor connected between RT pin and ground. The resistance value RT is calculated from Equation 6:

Equation 6. RT = (5725/F)1.026

where

  • F is in kHz and RT in kΩ

8.2.2.2 Soft-Start Ramp Time and Hiccup Interval

The soft-start ramp time and hiccup internal is programmed by a capacitor (CSS) on the SS pin to ground. The soft-start ramp time is determined by comparing the SS pin voltage with COMP pin voltage. When the SS voltage is less than COMP voltage, the COMP voltage is clamped by SS voltage. The PWM duty is limited by the clamped COMP voltage, so that soft start can be achieved. The first PWM pulse is generated after COMP voltage reaches 1 V. So the soft-start ramp time of the output voltage can be estimated by Equation 7:

Equation 7. LM5025A qu2new_nvsab0.gif

where

  • VSS is the steady-state COMP pin voltage. This voltage is determined by the output voltage, voltage divider, and the compensation network.

In hiccup mode, the SS current source is reduced to 1 µA. When the first PWM pulse is generated, the current source switches to 20 µA, and the power supply tries to start up again. The hiccup interval can be calculated by Equation 8:

Equation 8. LM5025A qu3new_nvsab0.gif

8.2.2.3 Feedforward Ramp and Maximum On-Time Clamp

An example illustrates the use of the Volt × Second Clamp comparator to achieve a 50% duty cycle limit, at
200 KHz, at a 48-V line input: A 50% duty cycle at a 200 KHz requires a 2.5 µs of ON-time. At 48-V input the Volt × Second product is 120 V × µs (48 V × 2.5 µs). To achieve this clamp level, see Equation 9 and Equation 10:

Equation 9. RFF × CFF = VIN × TON / 2.5 V
Equation 10. 48 × 2.5 µF / 2.5 = 48 µF

Select CFF = 470 pF

RFF = 102 kΩ

The recommended capacitor value range for CFF is 100 pF to 1000 pF.

8.2.2.4 Dead Times

The magnitude of the overlap and dead time can be calculated as follows in Equation 11 and Equation 12:

Equation 11. Overlap Time (ns) = 2.8 × RSET – 1.2
Equation 12. Dead Time (ns) = 2.9 × RSET + 20

where

  • RSET in kΩ, Time in ns
LM5025A PWM_outpus__nvsab0.gif Figure 15. PWM Outputs

8.2.3 Application Curves

LM5025A 20127607.gif
Conditions: input voltage = 48 VDC, output current = 5 A
Trace 1: output voltage Volts/div = 0.5 V
Horizontal resolution = 1 ms/div
Figure 16. Output Voltage During Typical Start-Up
LM5025A 20127609.gif
Conditions: input voltage = 48 VDC, output current = 30 A
Bandwidth limit = 25 MHz
Trace 1: output ripple voltage Volts/div = 50 mV
Horizontal resolution = 2 μs/div
Figure 18. Output Ripple
LM5025A 20127605.gif
Conditions: input voltage = 78 VDC, output current = 25 A
Trace 1: Q1 drain voltage Volts/div = 20 V
Horizontal resolution = 1 μs/div
Figure 20. Drain Voltage
LM5025A 20127608.gif
Conditions: input voltage = 48 VDC, output current = 5 A to 25 A
Trace 1: output voltage Volts/div = 0.5 V
Trace 2: output current, Amps/div = 10 A
Horizontal resolution = 1 μs/div
Figure 17. Transient Response
LM5025A 20127604.gif
Conditions: input voltage = 38 VDC, output current = 25 A
Trace 1: Q1 drain voltage Volts/div = 20 V
Horizontal resolution = 1 µs/div
Figure 19. Drain Voltage
LM5025A 20127606.gif
Conditions: input voltage = 48 VDC, output current = 5 A
Synchronous rectifier, Q3 gate Volts/div = 5 V
Trace 1: synchronous rectifier, Q3 gate Volts/div = 5 V
Trace 2: synchronous rectifier, Q5 gate Volts/div = 5 V
Horizontal resolution = 1 μs/div
Figure 21. Gate Voltages of the Synchronous Rectifiers

8.3 System Example

Figure 22 shows an application circuit with 36-V to 78-V input and 3.3-V, 30-A output capability.

LM5025A 20107417.png Figure 22. Application Circuit