SNVS963C SEPTEMBER   2013  – June 2016 LM5121 , LM5121-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings: LM5121
    3. 6.3 ESD Ratings: LM5121-Q1
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Undervoltage Lockout (UVLO)
      2. 7.3.2  High Voltage VCC Regulator
      3. 7.3.3  Oscillator
      4. 7.3.4  Slope Compensation
      5. 7.3.5  Error Amplifier
      6. 7.3.6  PWM Comparator
      7. 7.3.7  Disconnection Switch Control
      8. 7.3.8  Soft-Start
      9. 7.3.9  HO and LO Drivers
      10. 7.3.10 Bypass Operation (VOUT = VIN)
      11. 7.3.11 Cycle-by-Cycle Current Limit
      12. 7.3.12 Circuit Breaker Function
      13. 7.3.13 Clock Synchronization
      14. 7.3.14 Maximum Duty Cycle
      15. 7.3.15 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Hiccup Mode Short Circuit and Overload Protection
      2. 7.4.2 MODE Control (Forced PWM Mode and Diode Emulation Mode)
      3. 7.4.3 MODE Control (Skip Cycle Mode and Pulse Skipping Mode)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Feedback Compensation
      2. 8.1.2 Sub-Harmonic Oscillation
      3. 8.1.3 Output Overvoltage Protection
      4. 8.1.4 Input Transient Suppression
      5. 8.1.5 Inrush Current Limit Programming
      6. 8.1.6 Reverse Battery Protection + Disconnect Switch Control
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Timing Resistor RT
        2. 8.2.2.2  UVLO Divider RUV2, RUV1
        3. 8.2.2.3  Input Inductor LIN
        4. 8.2.2.4  Current Sense Resistor RS
        5. 8.2.2.5  Current Sense Filter RCSFP, RCSFN, CCS
        6. 8.2.2.6  Slope Compensation Resistor RSLOPE
        7. 8.2.2.7  Output Capacitor COUT
        8. 8.2.2.8  Input Capacitor CIN
        9. 8.2.2.9  VIN Filter RVIN, CVIN
        10. 8.2.2.10 Bootstrap Capacitor CBST and Boost Diode DBST
        11. 8.2.2.11 VCC Capacitor CVCC
        12. 8.2.2.12 Output Voltage Divider RFB1, RFB2
        13. 8.2.2.13 Soft-Start Capacitor CSS
        14. 8.2.2.14 Restart Capacitor CRES
        15. 8.2.2.15 Low-Side Power Switch QL
        16. 8.2.2.16 High-Side Power Switch QH and Additional Parallel Schottky Diode
        17. 8.2.2.17 Snubber Components
        18. 8.2.2.18 Disconnect Switch QD Selection
        19. 8.2.2.19 Freewheeling Diode DF Selection
        20. 8.2.2.20 Loop Compensation Components CCOMP, RCOMP, CHF
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

HTSSOP
PWP Package
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LM5121 LM5121-Q1 Device Info.gif

Pin Functions

PIN I/O(1) DESCRIPTION
NAME NO.
AGND 9 G Analog ground connection. Return for the internal voltage reference and analog circuits.
BST 20 P/I High-side driver supply for bootstrap gate drive. Connect to the cathode of the external bootstrap diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge the high-side N-channel MOSFET gate and should be placed as close to controller as possible. An internal BST charge pump will supply 200 µA current into bootstrap capacitor for bypass operation.
COMP 11 O Output of the internal error amplifier. The loop compensation network should be connected between this pin and the FB pin.
CSN 3 I Inverting input of current sense amplifier. Connect to the negative-side of the current sense resistor.
CSP 4 I Non-inverting input of current sense amplifier. Connect to the positive-side of the current sense resistor.
DG 2 O Disconnection switch control pin. Connect to the gate terminal of the N-channel MOSFET disconnection switch.
DS 1 I/O Source connection of N-channel MOSFET disconnection switch. Connect to the source terminal of the disconnection switch, the cathode terminal of the freewheeling diode and the supply input of boost inductor.
EP EP N/A Exposed pad of the package. No internal electrical connections. Should be soldered to the large ground plane to reduce thermal resistance.
FB 10 I Feedback. Inverting input of the internal error amplifier. A resistor divider from the output to this pin sets the output voltage level. The regulation threshold at the FB pin is 1.2 V.
HO 19 O High-side N-channel MOSFET gate drive output. Connect to the gate of the high-side synchronous N-channel MOSFET switch through a short, low inductance path.
LO 16 O Low-side N-channel MOSFET gate drive output. Connect to the gate of the low-side N-channel MOSFET switch through a short, low inductance path.
MODE 13 I Switching mode selection pin. Internal 700 kΩ pull-up and 100 kΩ pull-down resistor hold MODE pin to 0.15 V as a default. By adding external pull-up or pull-down resistor, MODE pin voltage can be programmed. When MODE pin voltage is greater than 1.2 V, diode emulation mode threshold, forced PWM mode is enabled, allowing current to flow in either direction through the high-side N-channel MOSFET switch. When MODE pin voltage is less than 1.2 V, the controller works in diode emulation mode. Skip cycle comparator is activated as a default condition when the MODE pin is left floating. If the MODE pin is grounded, the controller still operates in diode emulation mode, but the skip cycle comparator will not be triggered in normal operation, this enables pulse skipping operation at light load.
PGND 15 G Power ground connection pin for low-side N-channel MOSFET gate driver. Connect directly to the source terminal of the low-side N-channel MOSFET switch.
RES 14 O The restart timer pin for an external capacitor that configures hiccup mode off-time and restart delay during over load conditions and hiccup mode short circuit protection. Connect directly to the AGND when hiccup mode operation is not required.
SLOPE 12 I Slope compensation is programmed by an external resistor between SLOPE and the AGND.
SS 7 I Soft-start programming pin. An external capacitor and an internal 10 μA current source set the ramp rate of the internal error amplifier reference during soft-start.
SW 18 I/O Switching node of the boost regulator. Connect to the bootstrap capacitor, the source terminal of the high-side N-channel MOSFET switch and the drain terminal of the low-side N-channel MOSFET switch through short, low inductance paths.
SYNCIN/RT 8 I The internal oscillator frequency is programmed by an external resistor between RT and the AGND. The internal oscillator can be synchronized to an external clock by applying a positive pulse signal into this pin. The recommended maximum internal oscillator frequency is 2 MHz which leads to 1 MHz maximum switching frequency.
UVLO 6 I Undervoltage lockout programming pin. If the UVLO pin is below 0.4 V, the regulator is in the shutdown mode with all functions disabled. If the UVLO pin voltage is greater than 0.4 V and below 1.2 V, the regulator is in standby mode with the VCC regulator operational and no switching at the HO and LO outputs. If the UVLO pin voltage is above 1.2 V, the startup sequence begins. A 10 μA current source at UVLO pin is enabled when UVLO exceeds 1.2 V and flows through the external UVLO resistors to provide hysteresis. The UVLO pin should not be left floating.
VCC 17 P/O/I VCC bias supply pin. Locally decouple to PGND using a low ESR/ESL capacitor located as close to controller as possible.
VIN 5 P/I Supply voltage input source for the VCC regulator. Connect to the input capacitor and source power supply connection with short, low impedance paths.
(1) G = Ground, I = Input, O = Output, P = Power