JAJSJD3A June   2021  – June 2021 LM5146

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
    1. 6.1 Wettable Flanks
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Range (VIN)
      2. 8.3.2  Output Voltage Setpoint and Accuracy (FB)
      3. 8.3.3  High-Voltage Bias Supply Regulator (VCC)
      4. 8.3.4  Precision Enable (EN/UVLO)
      5. 8.3.5  Power Good Monitor (PGOOD)
      6. 8.3.6  Switching Frequency (RT, SYNCIN)
        1. 8.3.6.1 Frequency Adjust
        2. 8.3.6.2 Clock Synchronization
      7. 8.3.7  Configurable Soft Start (SS/TRK)
        1. 8.3.7.1 Tracking
      8. 8.3.8  Voltage-Mode Control (COMP)
      9. 8.3.9  Gate Drivers (LO, HO)
      10. 8.3.10 Current Sensing and Overcurrent Protection (ILIM)
      11. 8.3.11 OCP Duty Cycle Limiter
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
      4. 8.4.4 Diode Emulation Mode
      5. 8.4.5 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Design and Implementation
      2. 9.1.2 Power Train Components
        1. 9.1.2.1 Inductor
        2. 9.1.2.2 Output Capacitors
        3. 9.1.2.3 Input Capacitors
        4. 9.1.2.4 Power MOSFETs
      3. 9.1.3 Control Loop Compensation
      4. 9.1.4 EMI Filter Design
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – 12-A High-Efficiency Synchronous Buck DC/DC Regulator
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Custom Design With WEBENCH® Tools
        4. 9.2.1.4 Custom Design With Excel Quickstart Tool
        5. 9.2.1.5 Application Curves
      2. 9.2.2 Design 2 – High Density, 12-V, 8-A Rail From 48-V Telecom Power
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Stage Layout
      2. 11.1.2 Gate Drive Layout
      3. 11.1.3 PWM Controller Layout
      4. 11.1.4 Thermal Design and Layout
      5. 11.1.5 Ground Plane Design
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
        1. 12.2.1.1 PCB Layout Resources
        2. 12.2.1.2 Thermal Design Resources
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2.2 Detailed Design Procedure

A high power density, high-efficiency regulator solution uses 100-V power MOSFETs in SON 5-mm × 6-mm packages, together with a low-DCR inductor and all-ceramic capacitor design. The design occupies a footprint of 30 mm × 15 mm on a single-sided PCB. The overcurrent (OC) setpoint in this design is set at 12 A based on the resistor RILIM and the 10-mΩ RDS(on) of the low-side MOSFET (typical at TJ = 25°C and VGS = 10 V). The 12-V output is connected to VCC through a diode, D1, to reduce IC bias power dissipation at high input voltages.

The selected buck converter powertrain components are cited in Table 9-8, including power MOSFETs, buck inductor, input and output capacitors, and ICs. Using the LM5146 Quickstart Calculator, compensation components are selected based on a target loop crossover frequency of 40 kHz and phase margin greater than 55°. The output voltage soft-start time is 6 ms based on the selected soft-start capacitance, CSS, of 47 nF.

Table 9-8 List of Materials for Application Circuit 2
REFERENCE DESIGNATOR QTY SPECIFICATION MANUFACTURER PART NUMBER
CIN 5 2.2 µF, 100 V, X7R, 1210, ceramic TDK CGA6N3X7R2A225K
Taiyo Yuden HMK325B7225KM-P
2.2 µF, 100 V, X7S, 1206, ceramic Murata GCM31CC72A225KE02
COUT 5 22 µF, 25 V, X7R, 1210, ceramic TDK CGA6P3X7R1E226M
Murata GCM32EC71E226KE36
Taiyo Yuden TMK325B7226KMHT
LF 1 6.8 µH, 12 mΩ, 13.3 A, 10.85 × 10.0 × 5.2 mm Cyntec VCHA105D-6R8MS6
6.8 µH, 13.3 mΩ, 21.4 A, 10.5 × 10.0 × 6.5 mm TDK SPM10065VT-6R8M-D
Q1 1 100 V, 22 mΩ, MOSFET, SON 5 × 6 Onsemi NVMFS6B25NLT1G
Q2 1 100 V, 10 mΩ, MOSFET, SON 5 × 6 Onsemi NVMFS6B14NLT1G
U1 1 Wide VIN synchronous buck controller Texas Instruments LM5146RGYR

As shown in Figure 9-16, a 2.2-Ω resistor in series with CBST is used to slow the turn-on transition of the high-side MOSFET, reducing the spike amplitude and ringing of the SW node voltage and minimizing the possibility of Cdv/dt-induced shoot-through of the low-side MOSFET. If needed, place an RC snubber (for example, 2.2 Ω and 100 pF) close to the drain (SW node) and source (PGND) terminals of the low-side MOSFET to further attenuate any SW node voltage overshoot and/or ringing. Please refer to the application note Reduce Buck Converter EMI and Voltage Stress by Minimizing Inductive Parasitics for more detail.