JAJSJ65B May   2020  – June 2021 LM62435-Q1

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Systems Characteristics
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  EN Uses for Enable and VIN UVLO
      2. 8.3.2  MODE/SYNC Pin Operation
        1. 8.3.2.1 Level-Dependent MODE/SYNC Pin Control
        2. 8.3.2.2 Pulse-Dependent MODE/SYNC Pin Control
        3. 8.3.2.3 Clock Locking
      3. 8.3.3  PGOOD Output Operation
      4. 8.3.4  Internal LDO, VCC UVLO, and BIAS Input
      5. 8.3.5  Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
      6. 8.3.6  Adjustable SW Node Slew Rate
      7. 8.3.7  Spread Spectrum
      8. 8.3.8  Soft Start and Recovery From Dropout
      9. 8.3.9  Output Voltage Setting
      10. 8.3.10 Overcurrent and Short Circuit Protection
      11. 8.3.11 Thermal Shutdown
      12. 8.3.12 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 CCM Mode
        2. 8.4.3.2 Auto Mode - Light Load Operation
          1. 8.4.3.2.1 Diode Emulation
          2. 8.4.3.2.2 Frequency Reduction
        3. 8.4.3.3 FPWM Mode - Light Load Operation
        4. 8.4.3.4 Minimum On-time (High Input Voltage) Operation
        5. 8.4.3.5 Dropout
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Choosing the Switching Frequency
        2. 9.2.2.2  Setting the Output Voltage
        3. 9.2.2.3  Inductor Selection
        4. 9.2.2.4  Output Capacitor Selection
        5. 9.2.2.5  Input Capacitor Selection
        6. 9.2.2.6  BOOT Capacitor
        7. 9.2.2.7  BOOT Resistor
        8. 9.2.2.8  VCC
        9. 9.2.2.9  BIAS
        10. 9.2.2.10 CFF and RFF Selection
        11. 9.2.2.11 External UVLO
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground and Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Level-Dependent MODE/SYNC Pin Control

If only a single mode is used, the part can be configured using level-dependent control. Note that the LMQ6235-Q1 cannot be synchronized to an external clock signal in level-dependent mode. Table 8-1 shows a summary of level-dependent mode selection settings. The level-dependent mode selection setting registers after tMODE. The level-dependent mode summary is also depicted in Figure 8-2.

Table 8-1 Level-Dependent Mode Selection Settings
MODE/SYNC INPUT MODE
GND Auto Mode with Spread Spectrum
VCC OR > VMODE_H AND < VMODE_H2 FPWM Mode with Spread Spectrum
VIN OR > VMODE_H3 FPWM Mode without Spread Spectrum
GUID-4E56C95F-6FE5-44EA-A44B-C3B5EB3702D0-low.gif Figure 8-2 Level-Dependent Mode Selection Settings

Note that during dropout operation, the input voltage is close to VCC. Since this condition is typically seen while operating in dropout, frequency is typically folded back and spread spectrum is deactivated. When VIN increases and the device is no longer in frequency foldback, spread spectrum is reactivated. When the input voltage is between 3 V to 3.7 V and the LMQ6235-Q1 is not in dropout operation, the spread spectrum operation is not guaranteed.

One purpose of level-dependent MODE/SYNC pin control is to dynamically change between FPWM and Auto Mode. To ensure the resistance from MODE/SYNC to ground is < RSYNC_L, it is recommended to use 6 kΩ to ground. The MODE/SYNC pin can then be toggled between FPWM and Auto Mode as shown in Table 8-1.

If Auto Mode without spread spectrum operation is desired, tie the MODE/SYNC pin to ground through a 100-kΩ resistor. Auto Mode without spread spectrum is a fixed option, and the mode cannot be changed dynamically.