JAJSLG4 december   2022 LM7480

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Charge Pump
      2. 9.3.2 Dual Gate Control (DGATE, HGATE)
        1. 9.3.2.1 Reverse Battery Protection (A, C, DGATE)
        2. 9.3.2.2 Load Disconnect Switch Control (HGATE, OUT)
      3. 9.3.3 Overvoltage Protection and Battery Voltage Sensing (VSNS, SW, OV)
      4. 9.3.4 Low Iq Shutdown and Under Voltage Lockout (EN/UVLO)
    4. 9.4 Device Functional Modes
    5. 9.5 Application Examples
      1. 9.5.1 Redundant Supply OR-ing with Inrush Current Limiting, Overvoltage Protection and ON/OFF Control
      2. 9.5.2 Ideal Diode With Unsuppressed Load Dump Protection
  11. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical 12-V Reverse Battery Protection Application
      1. 10.2.1 Design Requirements for 12-V Battery Protection
      2. 10.2.2 Automotive Reverse Battery Protection
      3. 10.2.3 Detailed Design Procedure
        1. 10.2.3.1 Design Considerations
        2. 10.2.3.2 Charge Pump Capacitance VCAP
        3. 10.2.3.3 Input and Output Capacitance
        4. 10.2.3.4 Hold-Up Capacitance
        5. 10.2.3.5 Overvoltage Protection and Battery Monitor
      4. 10.2.4 MOSFET Selection: Blocking MOSFET Q1
      5. 10.2.5 MOSFET Selection: Hot-Swap MOSFET Q2
      6. 10.2.6 TVS Selection
      7. 10.2.7 Application Curves
    3. 10.3 200-V Unsuppressed Load Dump Protection Application
      1. 10.3.1 Design Requirements for 200-V Unsuppressed Load Dump Protection
      2. 10.3.2 Design Procedure
        1. 10.3.2.1 Boost Converter Components (C2, C3, L1)
        2. 10.3.2.2 Input and Output Capacitance
        3. 10.3.2.3 VS Capacitance, Resistor, and Zener Clamp
        4. 10.3.2.4 Overvoltage Protection and Output Clamp
        5. 10.3.2.5 MOSFET Q1 Selection
        6. 10.3.2.6 Input TVS Selection
        7. 10.3.2.7 MOSFET Q2 Selection
      3. 10.3.3 Application Curves
    4. 10.4 Do's and Don'ts
    5. 10.5 Power Supply Recommendations
      1. 10.5.1 Transient Protection
      2. 10.5.2 TVS Selection for 12-V Battery Systems
      3. 10.5.3 TVS Selection for 24-V Battery Systems
    6. 10.6 Layout
      1. 10.6.1 Layout Guidelines
      2. 10.6.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.6.1 Layout Guidelines

  • For the ideal diode stage, connect A, GATE and C pins of LM74720-Q1 close to the MOSFET's SOURCE, GATE and DRAIN pins.
  • The high current path of for this solution is through the MOSFET; therefore, it is important to use thick and short traces for source and drain of the MOSFET to minimize resistive losses.
  • The GATE pin of the LM74720-Q1 must be connected to the MOSFET GATE with short trace.
  • Boost converter switching currents flow into LX, CAP, GND pins and C3 (across DRAIN of the FET to GND). The loops formed by capacitor across CAP pin and DRAIN of the FET and C3 to GND must be minimized by placing these capacitors as close as possible. Keep the GND side of the C3 capacitor close to GND pin of LM74720-Q1.
  • Place transient suppression components like input TVS and output Schottky close to LM74720-Q1.