SNLS233O April   2007  – July 2015 LMH0344

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configurations and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 AC Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Block Description
      2. 7.3.2 Mute Reference (MuteREF)
      3. 7.3.3 Carrier Detect (CD) and Mute
      4. 7.3.4 Input Interfacing
      5. 7.3.5 Output Interfacing
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Dos and Don'ts
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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7 Detailed Description

7.1 Overview

The LMH0344 3-Gbps HD–SD SDI Adaptive Cable Equalizer is designed to equalize data transmitted over cable or any other media with similar dispersive loss characteristics. The equalizer operates over a wide range of data rates from 125 Mbps to 2.97 Gbps and supports ST 424, ST 292, ST 344, and ST 259.

7.2 Functional Block Diagram

LMH0344 20199002.gif

7.3 Feature Description

7.3.1 Block Description

The Equalizer Filter block is a multistage adaptive filter. If BYPASS is high, the equalizer filter is disabled.

The DC Restoration / Level Control block receives the differential signals from the equalizer filter block. This block incorporates a self-biasing DC restoration circuit to fully DC restore the signals. If BYPASS is high, this function is disabled.

The signals before and after the DC Restoration / Level Control block are used to generate the Automatic Equalization Control (AEC) signal. This control signal sets the gain and bandwidth of the equalizer filter. The loop response in the AEC block is controlled by an external 1-µF capacitor placed across the AEC+ and AEC– pins.

The Carrier Detect / Mute block generates the carrier detect signal and controls the mute function of the output. This block uses the CD and MUTE signals along with Mute Reference (MUTEREF).

The Output Driver produces SDO and SDO.

7.3.2 Mute Reference (MuteREF)

The mute reference sets the threshold for CD and (with CD tied to MUTE) determines the amount of cable to equalize before automatically muting the outputs. This is set by applying a voltage inversely proportional to the length of cable to equalize. The applied voltage must be greater than the MUTEREF floating voltage (typically 1.3 V) to change the CD threshold. As the applied MUTEREF voltage is increased, the amount of cable that can be equalized before carrier detect is deasserted and the outputs are muted is decreased. MUTEREF may be left unconnected or connected to ground for maximum equalization before muting.

7.3.3 Carrier Detect (CD) and Mute

Carrier detect CD indicates if a valid signal is present at the LMH0344 input. If MUTEREF is used, the carrier detect threshold will be altered accordingly. CD provides a high voltage when no signal is present at the LMH0344 input. CD is low when a valid input signal is detected.

MUTE can be used to manually mute or enable SDO and SDO. Applying a high input to MUTE will mute the LMH0344 outputs by forcing the output to a logic zero. Applying a low input will force the outputs to be active.

CD and MUTE may be tied together to automatically mute the output when no input signal is present.

7.3.4 Input Interfacing

The LMH0344 accepts either differential or single-ended input. The input must be AC-coupled. Transformer coupling is not supported.

The LMH0344 correctly handles equalizer pathological signals for standard definition and high definition serial digital video, as described in SMPTE RP 178 and RP 198, respectively.

7.3.5 Output Interfacing

The SDO and SDO outputs are internally loaded with 50 Ω. These outputs produce a 750-mVP-P differential output, or a 375-mVP-P single-ended output.

7.4 Device Functional Modes

The LMH0344 features can be programmed using pin mode only.