JAJSFM3E February   2015  – June 2018 LMH1218

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      SPI概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Descriptions – SPI Mode/ Mode_SEL = 1 kΩ to VDD
    2.     Pin Descriptions – SMBUS Mode/ MODE_SEL = 1 kΩ to GND
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Recommended SMBus Interface AC Timing Specifications
    7. 7.7 Serial Parallel Interface (SPI) Bus Interface AC Timing Specifications
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Loss of Signal Detector
      2. 8.3.2 Continuous Time Linear Equalizer (CTLE)
      3. 8.3.3 2:1 Multiplexer
      4. 8.3.4 Clock and Data Recovery
      5. 8.3.5 Eye Opening Monitor (EOM)
      6. 8.3.6 Fast EOM
        1. 8.3.6.1 SMBus Fast EOM Operation
        2. 8.3.6.2 SPI Fast EOM Operation
      7. 8.3.7 LMH1218 Device Configuration
        1. 8.3.7.1 MODE_SEL
        2. 8.3.7.2 ENABLE
        3. 8.3.7.3 LOS_INT_N
        4. 8.3.7.4 LOCK
        5. 8.3.7.5 SMBus MODE
        6. 8.3.7.6 SMBus READ/WRITE Transaction
        7. 8.3.7.7 SPI Mode
          1. 8.3.7.7.1 SPI READ/WRITE Transaction
          2. 8.3.7.7.2 SPI Write Transaction Format
          3. 8.3.7.7.3 SPI Read Transaction Format
        8. 8.3.7.8 SPI Daisy Chain
          1. 8.3.7.8.1 SPI Daisy Chain Write Example
          2. 8.3.7.8.2 SPI Daisy Chain Write Read Example
            1. 8.3.7.8.2.1 SPI Daisy Chain Length of Daisy Chain Illustration
      8. 8.3.8 Power-On Reset
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 Global Registers
      2. 8.6.2 Receiver Registers
      3. 8.6.3 CDR Registers
      4. 8.6.4 Transmitter Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 General Guidance for All Applications
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
    4. 9.4 Initialization Set Up
      1. 9.4.1 Selective Data Rate Lock
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Solder Profile
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

RTW Package
24-Pin WQFN
(Top View)
LMH1218 pin_configuration_2_16.gif

Pin Descriptions – SPI Mode/ Mode_SEL = 1 kΩ to VDD

PIN TYPE DESCRIPTION
NAME NO.
CONTROL/INDICATOR I/O
ENABLE 6 Input, 4-Level Powers down device when pulled low
1 kΩ to VDD:
  • Power down until valid signal detected

Float(Default):
  • Power down until valid signal detected

20 kΩ to GND:
  • Reserved

1 kΩ to GND:
  • Power down including signal detects and Reset Registers upon power-up
LOCK 16 Output, 2.5-V LVCMOS, 2-Level Indicates CDR lock detect status
High:
  • CDR locked

Low:
  • CDR not locked
LOS_INT_N 13 Output,
LVCMOS Open-Drain, 2-Level		 Programmable Interrupt caused by change in LOS, violation of internal eye monitor threshold, or change in lock. External 4.7-kΩ pullup resistor is required. This pin is 3.3-V LVCMOS tolerant.
MISO 15 Output, 2.5-V LVCMOS, 2-Level SPI Master Input / Slave Output. LMH1218 SPI data transmit
MODE_SEL 1 Input, 4-Level Determines Device Configuration: SPI or SMBus
1 kΩ to VDD:
MOSI 4 Input, 2-Level SPI Master Output / Slave Input. LMH1218 SPI data receive
RESERVED 5, 17, 18 — No Connect
SCK 3 Input, 2.5V LVCMOS, 2-Level SPI serial clock input
SMPTE_10GbE 14 — No Connect
SS_N 2 Input, 2-Level SPI Slave Select. This pin has internal pullup
HIGH-SPEED DIFFERENTIAL I/O
IN0+ 11 Input, Analog Inverting and noninverting differential inputs. An on-chip 100-Ω terminating resistor connects IN0+ to IN0-. Inputs require 4.7-µF, AC-coupling capacitors.
IN0– 12 Input, Analog
IN1+ 8 Input, Analog Inverting and noninverting differential inputs. An on-chip 100-Ω terminating resistor connects IN1+ to IN1-. Inputs require 4.7-µF, AC-coupling capacitors.
IN1– 9 Input, Analog
OUT0+ 20 Output, 75-Ω CML Compatible Inverting and noninverting 75-Ω outputs. An on-chip 75-Ω terminating resistor connects OUT0+ and OUT0- to VDD. Outputs require 4.7-µF, AC-coupling capacitors
OUT0– 19 Output, 75-Ω CML Compatible
OUT1+ 23 Output, Analog Inverting and noninverting differential outputs. An on-chip 100-Ω terminating resistor connects OUT1+ to OUT1-. Outputs require 4.7-µF, AC-coupling capacitors
OUT1– 22 Output, Analog
POWER
DAP — Ground Exposed DAP, connect to GND using at least 5 vias (see package drawing)
VDD 7, 21 2.5-V Supply 2.5 V ± 5%
VSS 10, 24 Ground Ground

Pin Descriptions – SMBUS Mode/ MODE_SEL = 1 kΩ to GND

PIN TYPE DESCRIPTION
NAME NO.
ADDR0 2 Input, 4-Level 4-level strap pins used to set the SMBus address of the device. The pin state is read on power-up. The multi-level nature of these pins allows for 16 unique device addresses. Note the SMBus section for further details. The four strap options include:
1 kΩ to VDD:
  • Represents logic state 11’b

Float(Default): Represents logic state 10'b 7-bits SMBus address = 0x17
20 kΩ to GND:
  • Represents logic state 01'b

1 kΩ to GND:
  • Represents logic state 00'b
ADDR1 15
ENABLE 6 Input, 4-Level Powers down device when pulled low
1 kΩ to VDD:
  • Power down until valid signal detected

Float(Default): Reserved
20 kΩ to GND:
  • Reserved

1 kΩ to GND:
  • Power down including signal detects and Reset Registers upon power-up
LOCK 16 Output, 2.5-V LVCMOS, 2-Level Indicates CDR lock Status
High:
  • CDR locked

Low:
  • CDR not locked
LOS_INT_N 13 Output, LVCMOS
Open-Drain, 2-Level 		Programmable Interrupt caused by change in LOS, violation of internal eye monitor threshold, change in lock. External 4.7-kΩ pullup resistor is required. This pin is 3.3-V LVCMOS tolerant.
MODE_SEL 1 Input, 4-Level Determines Device Configuration: SPI or SMBus
1 kΩ to GND: SMBUS mode. See Initialization Set Up
RESERVED 5, 17, 18 — No Connect
SCL 3 Input, 2-Level SMBus clock input / open-drain. External 2-kΩ to 5-kΩ pullup resistor is required as per SMBus interface standard. This pin is 3.3-V LVCMOS tolerant.
SDA 4 I/O, Open-Drain, 2-Level SMBus data input / open-drain. External 2-kΩ to 5-kΩ pullup resistor is required as per SMBus interface standard. This pin is 3.3-V LVCMOS tolerant.
SMPTE_10GbE 14 No Connect
HIGH-SPEED DIFFERENTIAL I/O
DAP — Ground Exposed DAP, connect to GND using at least 5 vias (see package drawing)
IN0+ 11 Input, Analog Inverting and noninverting differential inputs. An on-chip 100-Ω terminating resistor connects IN0+ to IN0–. Inputs require 4.7-µF, AC-coupling capacitors.
IN0– 12 Input, Analog
IN1+ 8 Input, Analog Inverting and noninverting differential inputs. An on-chip 100-Ω terminating resistor connects IN0+ to IN0–. Inputs require 4.7-µF, AC-coupling capacitors.
IN1– 9 Input, Analog
OUT0+ 20 Output, 75-Ω CML Compatible Inverting and noninverting 75-Ω outputs. An on-chip 75-Ω terminating resistor connects OUT0+ and OUT0– to VDD. Outputs require 4.7-µF, AC-coupling capacitors
OUT0– 19 Output, 75-Ω CML Compatible
OUT1+ 23 Output, Analog Inverting and noninverting differential outputs. An on-chip 100 Ω terminating resistor connects OUT1+ to OUT1–. Outputs require 4.7-µF, AC-coupling capacitors
OUT1– 22 Output, Analog
VDD 7, 21 2.5-V Supply 2.5 V ± 5%
VSS 10, 24 Ground Ground