JAJSGV2D January   2012  – September 2021 LMK01801

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Functional Configurations
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Recommended Operating Conditions
    3. 7.3 Thermal Information
    4. 7.4 Electrical Characteristics
    5. 7.5 Serial MICROWIRE Timing Diagram
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Differential Voltage Measurement Terminology
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  High-Speed Clock Inputs (CLKin0/CLKin0* and CLKin1/CLKin1*)
      2. 9.3.2  Clock Distribution
      3. 9.3.3  Small Divider (1 to 8)
      4. 9.3.4  Large Divider (1 to 1045)
      5. 9.3.5  CLKout Analog Delay
      6. 9.3.6  CLKout0 to CLKout11 Digital Delay
      7. 9.3.7  CLKout12 and CLKout13 Digital Delay
      8. 9.3.8  Programmable Outputs
      9. 9.3.9  Clock Output Synchronization
      10. 9.3.10 Default Clock Outputs
    4. 9.4 Device Functional Modes
      1. 9.4.1 Programmable Mode
      2. 9.4.2 Pin Control Mode
      3. 9.4.3 Inputs / Outputs
        1. 9.4.3.1 CLKin0 and CLKin1
      4. 9.4.4 Input and Output Dividers
      5. 9.4.5 Fixed Digital Delay
        1. 9.4.5.1 Fixed Digital Delay - Example
      6. 9.4.6 Clock Output Synchronization (SYNC)
        1. 9.4.6.1 Dynamically Programming Digital Delay
          1. 9.4.6.1.1 Relative Dynamic Digital Delay
          2. 9.4.6.1.2 Relative Dynamic Digital Delay - Example
    5. 9.5 Programming
      1. 9.5.1 Recommended Programming Sequence
        1. 9.5.1.1 Overview
    6. 9.6 Register Map
      1. 9.6.1 Default Device Register Settings After Power On/Reset
      2. 9.6.2 Register R0
        1. 9.6.2.1 RESET
        2. 9.6.2.2 POWERDOWN
        3. 9.6.2.3 CLKoutX_Y_PD
          1. 9.6.2.3.1 CLKinX_BUF_TYPE
          2. 9.6.2.3.2 CLKinX_DIV
          3. 9.6.2.3.3 CLKinX_MUX
      3. 9.6.3 Register R1 and R2
        1. 9.6.3.1 CLKoutX_TYPE
      4. 9.6.4 Register R3
        1. 9.6.4.1 CLKout12_13_ADLY
        2. 9.6.4.2 CLKout12_13_HS, Digital Delay Half Shift
        3. 9.6.4.3 SYNC1_QUAL
        4. 9.6.4.4 SYNCX_POL_INV
        5. 9.6.4.5 NO_SYNC_CLKoutX_Y
        6. 9.6.4.6 CLKoutX_Y_OFFSET_PD
        7. 9.6.4.7 SYNCX_FAST
        8. 9.6.4.8 SYNCX_AUTO
      5. 9.6.5 Register R4
        1. 9.6.5.1 CLKout12_13_DDLY, Clock Channel Digital Delay
      6. 9.6.6 Register R5
        1. 9.6.6.1 CLKout12_ADLY_SEL[13], CLKout13_ADLY_SEL[14], Select Analog Delay
        2. 9.6.6.2 CLKoutX_Y_DIV Clock Output Divide
      7. 9.6.7 Register 15
        1. 9.6.7.1 uWireLock
  10. 10Application and Implementation
    1. 10.1 Typical Application
      1. 10.1.1 Detailed Design Procedure
        1. 10.1.1.1 Driving CLKin Inputs
          1. 10.1.1.1.1 Driving CLKin Pins With a Differential Source
          2. 10.1.1.1.2 Driving CLKin Pins With a Single-Ended Source
        2. 10.1.1.2 Termination and Use of Clock Output (Drivers)
          1. 10.1.1.2.1 Termination for DC-Coupled Differential Operation
          2. 10.1.1.2.2 Termination for AC-Coupled Differential Operation
          3. 10.1.1.2.3 Termination for Single-Ended Operation
  11. 11Power Supply Recommendations
    1. 11.1 Current Consumption
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Pin Connection Recommendations
        1. 12.1.1.1 Vcc Pins and Decoupling
        2. 12.1.1.2 Unused clock outputs
        3. 12.1.1.3 Unused clock inputs
        4. 12.1.1.4 Unused GPIO (CLKoutTYPE_X)
        5. 12.1.1.5 Bias
        6. 12.1.1.6 In MICROWIRE Mode
    2. 12.2 Thermal Management
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-A1DFD96E-9684-4F67-80F2-A16538F8B6F8-low.gif Figure 6-1 48-Pin Package
Table 6-1 Pin Functions(1)
Pin Number Name(s) I/O Type Description
1 LEuWire/
CLKoutDIV_2		 I CMOS / 3-State MICROWIRE Latch Enable Input /
Pin control mode: clock divider 2
2, 3 CLKout0,
CLKout0*		 O Programmable Clock output 0: LVDS or LVPECL
4, 5 CLKout1*,
CLKout1		 O Programmable Clock output 1: LVDS or LVPECL
6 Vcc1_CLKout
0_1_2_3		 I PWR Power supply for clock outputs 0, 1, 2, and 3
7, 8 CLKout2,
CLKout2*		 O Programmable Clock output 2: LVDS or LVPECL
9, 10 CLKout3*,
CLKout3		 O Programmable Clock output 3: LVDS or LVPECL
11 Test/
CLKoutTYPE_0		 I/O CMOS / 3-State Reserved Test Pin /
Pin control mode: clock output type select 0
12 SYNC0/
CLKoutTYPE_1		 I CMOS / 3-State SYNC0 / Pin control mode: clock output type select 1
13, 14 CLKin0,
CLKin0*		 I ANLG Clock input 0. Supports clocking types including but not limited to LVDS, LVPECL, and LVCMOS
15 Vcc2_CLKin0 I PWR Power supply for clock input 0
16, 17 CLKout4,
CLKout4*		 O Programmable Clock output 4: LVDS, LVPECL, or LVCMOS
18, 19 CLKout5*,
CLKout5		 O Programmable Clock output 5: LVDS, LVPECL, or LVCMOS
20 Vcc3_CLKout
4_5_6_7		 I PWR Power supply for clock outputs 4, 5, 6, and 7
21, 22 CLKout6,
CLKout6*		 O Programmable Clock output 6: LVDS, LVPECL, or LVCMOS
23, 24 CLKout7*,
CLKout7		 O Programmable Clock output 7: LVDS, LVPECL, or LVCMOS
25 Vcc4_Bias I PWR Power supply for Bias
26 Bias ANLG Bias bypass pin
27 EN_PIN_CTRL I 3-State Select MICROWIRE or pin control mode
28, 29 CLKout8,
CLKout8*		 O Programmable Clock output 8: LVDS, LVPECL, or LVCMOS
30, 31 CLKout9*,
CLKout9		 O Programmable Clock output 9: LVDS, LVPECL, or LVCMOS
32 Vcc5_CLKout
8_9_10_11		 I PWR Power supply for clock outputs 8, 9, 10, and 11
33, 34 CLKout10,
CLKout10*		 O Programmable Clock output 10: LVDS, LVPECL, or LVCMOS
35, 36 CLKout11*,
CLKout11		 O Programmable Clock output 11: LVDS, LVPECL, or LVCMOS
37 Vcc6_CLKin1 I PWR Power supply for clock input 1
38, 39 CLKin1,
CLKin1*		 I ANLG Clock input 1. Supports clocking types including but not limited to LVDS, LVPECL, and LVCMOS
40 SYNC1/
CLKoutTYPE_2		 I CMOS / 3-State SYNC pin for CLKin1 and bank B.
Pin control mode: Clock output type select 2
41 Vcc7_CLKout
12_13		 I PWR Power supply for clock outputs 12, and 13
42, 43 CLKout12,
CLKout12*		 O Programmable Clock output 12: LVDS, LVPECL, or LVCMOS
44, 45 CLKout13*,
CLKout13		 O Programmable Clock output 13: LVDS, LVPECL, or LVCMOS
46 Vcc8_DIG I PWR Power supply for digital
47 DATAuWire/
CLKoutDIV_0		 I CMOS / 3-State MICROWIRE DATA Pin / Pin control mode: Clock divider 0
48 CLKuWire/
CLKoutDIV_1		 I CMOS / 3-State MICROWIRE CLK Pin / Pin control mode: Clock divider 1
DAP DAP GND DIE ATTACH PAD, connect to GND
(1) See Section 12.1.1 for recommended connections.