JAJSME4 November   2023 LMR36500

PRODMIX  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD (Commercial) Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable, Shutdown, and Start-up
      2. 7.3.2 Adjustable Switching Frequency (with RT)
      3. 7.3.3 Power-Good Output Operation
      4. 7.3.4 Internal LDO, VCC UVLO, and VOUT/FB Input
      5. 7.3.5 Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
      6. 7.3.6 Output Voltage Selection
      7. 7.3.7 Soft Start and Recovery from Dropout
        1. 7.3.7.1 Soft Start
        2. 7.3.7.2 Recovery from Dropout
      8. 7.3.8 Current Limit and Short Circuit
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 AUTO Mode - Light Load Operation
          1. 7.4.3.2.1 Diode Emulation
          2. 7.4.3.2.2 Frequency Reduction
        3. 7.4.3.3 FPWM Mode - Light Load Operation
        4. 7.4.3.4 Minimum On-time Operation
        5. 7.4.3.5 Dropout
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Choosing the Switching Frequency
        2. 8.2.2.2  Setting the Output Voltage
          1. 8.2.2.2.1 VOUT / FB for Adjustable Output
        3. 8.2.2.3  Inductor Selection
        4. 8.2.2.4  Output Capacitor Selection
        5. 8.2.2.5  Input Capacitor Selection
        6. 8.2.2.6  CBOOT
        7. 8.2.2.7  VCC
        8. 8.2.2.8  CFF Selection
        9. 8.2.2.9  External UVLO
        10. 8.2.2.10 Maximum Ambient Temperature
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Ground and Thermal Considerations
      2. 8.5.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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発注情報

Dropout

Dropout operation is defined as any input-to-output voltage ratio that requires frequency to drop to achieve the required duty cycle. At a given clock frequency, duty cycle is limited by minimum off-time. After this limit is reached as shown in Figure 7-19 if clock frequency is maintained, the output voltage falls. Instead of allowing the output voltage to drop, the LMR36500 extends the high side switch on-time past the end of the clock cycle until the needed peak inductor current is achieved. The clock is allowed to start a new cycle after peak inductor current is achieved or after a pre-determined maximum on-time, tON-MAX. As a result, after the needed duty cycle cannot be achieved at the selected clock frequency due to the existence of a minimum off-time, tOFF-MIN, frequency drops to maintain regulation. As shown in Figure 7-18 if input voltage is low enough so that output voltage cannot be regulated even with an on-time of tON-MAX, output voltage drops to slightly below the input voltage by VDROP. For additional information on recovery from dropout, refer back to Section 7.3.7.2.

The dropout performance of any buck regulator is affected by the RDSON of the power MOSFETs, the DC resistance of the inductor, and the maximum duty cycle that the controller can achieve. As mentioned, this device automatically reduces the switching frequency to maximize the effective duty-cycle in drop-out mode. There are two definitions of dropout voltage used in this data sheet. For both definitions, the dropout voltage is the difference between the input and output voltage under a specific condition. For the first definition, the difference is taken when the switching frequency just begins to drops. For this condition, the output voltage is within regulation. For the second definition, the difference is taken when the output voltage has fallen by 1% of the nominal regulation value. In this condition, the switching frequency has reached the lower limit. The lower frequency limit can be calculated using Equation 5. While the maximum effective duty cycle is calculated using Equation 6. For detailed drop-out calculations, contact your TI representative.

Equation 5. F M I N = 1 T O N - M A X + T O F F - M I N
Equation 6. D M A X = T O N - M A X T O N - M A X + T O F F - M I N
GUID-20230113-SS0I-PVH1-7R9R-ZQKQSP0FG9FJ-low.svg
Output voltage and frequency versus input voltage: If there is little difference between input voltage and output voltage setting, the IC reduces frequency to maintain regulation. If input voltage is too low to provide the desired output voltage at approximately 110 kHz, input voltage tracks output voltage.
Figure 7-18 Frequency and Output Voltage in Dropout
GUID-20220211-SS0I-M9BM-VPLC-J52JVVSQT2ZZ-low.svg
Switching waveforms while in dropout. Inductor current takes longer than a normal clock to reach the desired peak value. As a result, frequency drops. This frequency drop is limited by tON-MAX.
Figure 7-19 Dropout Waveforms