JAJS706K April   2000  – August 2016 LMV710-N

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
  4. 改訂履歴
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - 2.7 V
    6. 6.6 Electrical Characteristics - 3.2 V
    7. 6.7 Electrical Characteristics - 5 V
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Supply Bypassing
      2. 7.3.2 Shutdown Mode
      3. 7.3.3 Rail-to-Rail Input
    4. 7.4 Device Functional Modes
      1. 7.4.1 Compensation of Input Capacitance
      2. 7.4.2 Capacitive Load Tolerance
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 High-Side Current-Sensing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Peak Detector
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 GSM Power Amplifier Control Loop
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 関連リンク
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 コミュニティ・リソース
    6. 11.6 商標
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LMV71x family of amplifiers features low voltage, low power, and rail-to-rail output operational amplifiers designed for low-voltage portable applications.

8.2 Typical Applications

8.2.1 High-Side Current-Sensing

LMV710-N LMV711-N LMV715-N 30185616.gif Figure 41. High-Side, Current-Sensing Schematic

8.2.1.1 Design Requirements

The high-side, current-sensing circuit (Figure 41) is commonly used in a battery charger to monitor charging current to prevent over charging. A sense resistor RSENSE is connected to the battery directly. This system requires an op amp with rail-to-rail input. The LMV71x are ideal for this application because its common-mode input range goes up to the rail.

8.2.1.2 Detailed Design Procedure

As seen in (Figure 41), the ICHARGE current flowing through sense resistor RSENSE develops a voltage drop equal to VSENSE. The voltage at the negative sense point is now less than the positive sense point by an amount proportional to the VSENSE voltage.

The low-bias currents of the LMV71x cause little voltage drop through R2, so the negative input of the LMV71x amplifier is at essentially the same potential as the negative sense input.

The LMV71x detects this voltage error between its inputs and servo the transistor base to conduct more current through Q1, increasing the voltage drop across R1 until the LMV71x inverting input matches the noninverting input. At this point, the voltage drop across R1 now matches VSENSE.

IG, a current proportional to ICHARGE, flows according to Equation 3.

Equation 3. IG = VRSENSE / R1 = ( RSENSE × ICHARGE ) / R1

IG also flows through the gain resistor R3 developing a voltage drop equal to Equation 4.

Equation 4. V3 = IG × R3 = ( VRSENSE / R1 ) × R3 = ( ( RSENSE × ICHARGE ) / R2 ) × R3
Equation 5. VOUT = (RSENSE × ICHARGE ) × G

where

  • G = R3 / R1

The other channel of the LMV71x may be used to buffer the voltage across R3 to drive the following stages.

8.2.1.3 Application Curve

LMV710-N LMV711-N LMV715-N CUR_SENSE_TYP.png Figure 42. High-Side Current-Sensing Results

8.2.2 Peak Detector

LMV710-N LMV711-N LMV715-N 10132523.gif Figure 43. Peak Detector

8.2.2.1 Design Requirements

A peak detector outputs a DC voltage equal to the peak value of the applied AC signal. Peak detectors are used in many applications, such as test equipment, measurement instrumentation, ultrasonic alarm systems, and so forth. Figure 43 shows the schematic diagram of a peak detector using LMV71x-N. This peak detector basically consists of a clipper, a parallel RC network, and a voltage follower.

8.2.2.2 Detailed Design Procedure

An AC voltage source applied to VIN charges capacitor C1 to the peak of the input. Diode D1 conducts positive half cycles, charging C1 to the waveform peak. Including D1 inside the feedback loop of the amplifier removes the voltage drop of D1 and allows an accurate peak detection of VIN on C1. When the input waveform falls below the DC peak stored on C1, D1 is reverse biased. The low input bias current of A1 and the reverse biasing of D1 limits current leakage from C1. As a result, C1 retains the peak value even as the waveform drops to zero. A2 further isolates the peak value on C1 while completing the peak detector circuit by operating as a voltage follower and reporting the peak voltage of C1 at its output.

R5 and C1 are properly selected so that the capacitor is charged rapidly to VIN. During the holding period, the capacitor slowly discharge through C1, through leakage of the capacitor and the reverse-biased diode, or op amp bias currents. In any cases the discharging time constant is much larger than the charge time constant. And the capacitor can hold its voltage long enough to minimize the output ripple.

Resistors R2 and R3 limit the current into the inverting input of A1 and the noninverting input of A2 when power is disconnected from the circuit. The discharging current from C1 during power off may damage the input circuitry of the op amps.

The peak detector is reset by applying a positive pulse to the reset transistor. The charge on the capacitor is dumped into ground, and the detector is ready for another cycle.

The maximum input voltage to this detector must be less than (V+ – VD), where VD is the forward voltage drop of the diode. Otherwise, the input voltage must be scaled down before applying to the circuit.

8.2.3 GSM Power Amplifier Control Loop

LMV710-N LMV711-N LMV715-N 10132506.gif Figure 44. GSM P.A. Control Loop

8.2.3.1 Design Requirements

The control loop in Figure 44 controls the output power level of a GSM mobile phones. The control loop is used to avoid intermodulation of Base Station receivers, to prevent intermodulation with other mobile phones, and to minimize power consumption depending on the distance between mobile and base station

8.2.3.2 Detailed Design Procedure

There are four critical sections in the GSM Power Amplifier Control Loop. The class-C RF power amplifier provides amplification of the RF signal. A directional coupler couples small amount of RF energy from the output of the RF P. A. to an envelope detector diode. The detector diode senses the signal level and rectifies it to a DC level to indicate the signal strength at the antenna. An op amp is used as an error amplifier to process the diode voltage and ramping voltage. This loop control the power amplifier gain through the op amp and forces the detector diode voltage and ramping voltage to be equal. Power control is accomplished by changing the ramping voltage.

The LMV71x-N are well suited as an error amplifier in this application. The LMV711 or LMV715 have an extra shutdown pin to switch the op amp to shutdown mode. In shutdown mode, the LMV711 or LMV715 consume very low current. The LMV711 provides a ground voltage to the power amplifier control pin VPC. Therefore, the power amplifier can be turned off to save battery life. The LMV715 output is tri-stated when in shutdown.