SNVS649I January   2010  – October 2015 LMZ14201


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
      1. 7.1.1 COT Control Circuit Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Overvoltage Comparator
      2. 7.3.2 Current Limit
      3. 7.3.3 Thermal Protection
      4. 7.3.4 Zero Coil Current Detection
      5. 7.3.5 Prebiased Start-Up
    4. 7.4 Device Functional Modes
      1. 7.4.1 Discontinuous Conduction and Continuous Conduction Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Design Steps for the LMZ14201 Application
          1. Enable Divider, RENT and RENB Selection
          2. Output Voltage Selection
          3. Soft-Start Capacitor Selection
          4. CO Selection
          5. CIN Selection
          6. RON Resistor Selection
            1. Discontinuous Conduction and Continuous Conduction Mode Selection
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Module SMT Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation and Board Thermal Requirements
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information



10 Layout

10.1 Layout Guidelines

PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules.

  1. Minimize area of switched current loops.From an EMI reduction standpoint, it is imperative to minimize the high di/dt paths during PCB layout. The high current loops that do not overlap have high di/dt content that will cause observable high-frequency noise on the output pin if the input capacitor (Cin1) is placed at a distance away from the LMZ14201. Therefore place CIN1 as close as possible to the LMZ14201 VIN and GND exposed pad. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input and output capacitor should consist of a localized top side plane that connects to the GND exposed pad (EP).
  2. Have a single point ground.The ground connections for the feedback, soft-start, and enable components should be routed to the GND pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. Provide the single point ground connection from pin 4 to EP.
  3. Minimize trace length to the FB pin.Both feedback resistors, RFBT and RFBB, and the feed forward capacitor CFF, should be close to the FB pin. Because the FB node is high impedance, maintain the copper area as small as possible. The trace are from RFBT, RFBB, and CFF should be routed away from the body of the LMZ14201 to minimize noise.
  4. Make input and output bus connections as wide as possible.This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing so will correct for voltage drops and provide optimum output accuracy.
  5. Provide adequate device heat-sinking.Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to inner layer heat-spreading ground planes. For best results use a 6 × 6 via array with minimum via diameter of 8 mils thermal vias spaced 59 mils (1.5 mm). Ensure enough copper area is used for heat-sinking to keep the junction temperature below 125°C.

10.1.1 Power Module SMT Guidelines

The recommendations below are for a standard module surface mount assembly

  • Land Pattern – Follow the PCB land pattern with either soldermask defined or non-soldermask defined pads
  • Stencil Aperture
    • For the exposed die attach pad (DAP), adjust the stencil for approximately 80% coverage of the PCB land pattern
    • For all other I/O pads use a 1:1 ratio between the aperture and the land pattern recommendation
  • Solder Paste – Use a standard SAC Alloy such as SAC 305, type 3 or higher
  • Stencil Thickness – 0.125 to 0.15 mm
  • Reflow - Refer to solder paste supplier recommendation and optimized per board size and density
  • Refer to AN SNAA214 for Reflow information
  • Maximum number of reflows allowed is one
LMZ14201 reflow_chart_snvs632.png Figure 38. Sample Reflow Profile

Table 3. Sample Reflow Profile Table

1 242.5 6.58 0.49 6.39 0.00 0.00
2 242.5 7.10 0.55 6.31 0.00 7.10 0.00
3 241.0 7.09 0.42 6.44 0.00 0.00

10.2 Layout Example

LMZ14201 30114611.gif Figure 39. Minimize Area of Current Loops in Buck Module
LMZ14201 LMZ1420X_Layout.gif Figure 40. PCB Layout Guide
LMZ14201 30114616.png Figure 41. EVM Board Layout - Top View
LMZ14201 30114617.png Figure 42. EVM Board Layout - Bottom View

10.3 Power Dissipation and Board Thermal Requirements

For the design case of VIN = 24 V, VO = 3.3 V, IO = 1A, TAMB(MAX) = 85°C , and TJUNCTION = 125°C, the device must see a thermal resistance from case to ambient of less than:

Equation 18. RθCA< (TJ-MAX – TAMB(MAX)) / PIC-LOSS – RθJC

Given the typical thermal resistance from junction to case to be 1.9 °C/W. Use the 85°C power dissipation curves in the Typical Performance Characteristics section to estimate the PIC-LOSS for the application being designed. In this application it is 0.52W.

Equation 19. RθCA = (125 — 85) / 0.52 W — 1.9 = 75

To reach RθCA = 75, the PCB is required to dissipate heat effectively. With no airflow and no external heat, a good estimate of the required board area covered by 1 oz. copper on both the top and bottom metal layers is:

Equation 20. Board Area_cm2 = 500°C x cm2/W / RθJC

As a result, approximately 6 square cm of 1 oz copper on top and bottom layers is required for the PCB design. Additional area will decrease die temperature proportionately. The PCB copper heat sink must be connected to the exposed pad. Approximately thirty six, 8 mils thermal vias spaced 59 mils (1.5 mm) apart must connect the top copper to the bottom copper. For an example of a high thermal performance PCB layout of approximately 31 square cm area. Refer to the Evaluation Board application note AN-2024 SNVA422. For more information on thermal design see AN-2020 SNVA419 and AN-2026 SNVA424.