SNVS086K May   2000  – July 2015 LP2989LV

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 High-Accuracy Output Voltage
      2. 7.3.2 Sleep Mode
      3. 7.3.3 Error Detection Comparator Output
      4. 7.3.4 Short Circuit Protection (Current Limit)
      5. 7.3.5 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With 16 V ≥ VIN > VOUT(TARGET) + 1 V
      2. 7.4.2 Operation with Shutdown Control
      3. 7.4.3 Shutdown Input Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 WSON Package Devices
        2. 8.2.2.2 External Capacitors
          1. 8.2.2.2.1 Input Capacitor
          2. 8.2.2.2.2 Output Capacitor
          3. 8.2.2.2.3 Noise Bypass Capacitor
        3. 8.2.2.3 Capacitor Characteristics
          1. 8.2.2.3.1 Ceramic
          2. 8.2.2.3.2 Tantalum
          3. 8.2.2.3.3 Film
        4. 8.2.2.4 Reverse Input-Output Voltage
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

If Military/Aerospace specified devices are required contact the Texas Instruments Sales Office/Distributors for availability and specifications.(1)
MIN MAX UNIT
Operating junction temperature –40 125 °C
Power dissipation(2) Internally limited
Input supply voltage, survival –0.3 16 V
SENSE pin –0.3 6 V
Output voltage, survival(3) –0.3 16 V
IOUT, Survival Short-circuit protected
Input-output voltage, survival(4) –0.3 16 V
Storage temperature range, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal resistance, RθJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: P(MAX) = (TJ(MAX) – TA) / RθJA. The value RθJA for the WSON (NGN) package is specifically dependent on PCB trace area, trace material, and the number of layers and thermal vias. For improved thermal resistance and power dissipation for the WSON package, refer to Application Note AN-1187 Leadless Leadframe Package (LLP) (SNOA401). Exceeding the maximum allowable power dissipation causes excessive die temperature, and the regulator goes into thermal shutdown.
(3) If used in a dual-supply system where the regulator load is returned to a negative supply, the LP2989LV output must be diode-clamped to ground.
(4) The output PNP structure contains a diode between the IN and OUT pins that is normally reverse-biased. Forcing the output above the input turns on this diode and may induce a latch-up mode which can damage the part.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Operating junction temperature –40 125 °C
Operating input supply voltage 2.1 16 V

6.4 Thermal Information

THERMAL METRIC(1) LP2989LV UNIT
NGN (WSON) D (SOIC)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance, High-K 34.8  114.5  °C/W
RθJC(top) Junction-to-case (top) thermal resistance 28.4  61.1  °C/W
RθJB Junction-to-board thermal resistance 12.0  55.6  °C/W
ψJT Junction-to-top characterization parameter 0.2  9.7  °C/W
ψJB Junction-to-board characterization parameter 12.2  54.9  °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.3  n/a  °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Unless otherwise specified: TJ = 25°C, VIN = VOUT(NOM) + 1 V, IOUT = 1 mA, COUT = 4.7 µF, CIN = 2.2 µF, VSD = 2 V.
PARAMETER TEST CONDITIONS LP2989LVAI-X.X(1) LP2989LVI-X.X(1) UNIT
MIN TYP MAX MIN TYP MAX
VOUT Output voltage tolerance −0.75 0.75 −1.25 1.25 %VNOM
1 mA < IOUT < 500 mA, VOUT(NOM) + 1 V ≤ VIN ≤ 16 V −1.5 1.5 −2.5 2.5
1 mA < IOUT < 500 mA, VOUT(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C −4 2.5 −5 3.5
1 mA < IOUT < 500 mA, VOUT(NOM) + 1 V ≤ VIN ≤ 16 V, −25°C ≤ TJ ≤ 125°C −3.5 2.5 −4.5 3.5
ΔVOUT/ΔVIN Output voltage line regulation VOUT(NOM) + 1 V ≤ VIN ≤ 16 V 0.005 0.014 0.005 0.014 %/V
VOUT(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C 0.005 0.032 0.005 0.032
ΔVOUT/ΔIOUT Load regulation 1 mA < IOUT < 500 mA 0.4 0.4 %VNOM
VIN (minimum) Minimum input voltage required to maintain output regulation VOUT = 1.8 V
IOUT = 100 µA		 1.96 1.96 V
VOUT = 1.8 V
IOUT = 250 µA		 1.98 1.98
VOUT = 1.8 V
IOUT = 500 µA		 2.11 2.11
IGND Ground pin current IOUT = 100 µA 110 175 110 175 µA
IOUT = 100 µA, –40°C ≤ TJ ≤ 125°C 110 200 110 200
IOUT= 200 mA 1 2 1 2 mA
IOUT = 200 mA, –40°C ≤ TJ ≤ 125°C 1 3.5 1 3.5
IOUT = 500 mA 3 6 3 6 mA
IOUT = 500 mA, –40°C ≤ TJ ≤ 125°C 3 9 3 9
VSD < 0.18 V, –40°C ≤ TJ ≤ 125°C 0.5 2 0.5 2 µA
VSD < 0.4 V 0.05 0.8 0.05 0.8
IOUT(PK) Peak output current VOUT ≥ VOUT(NOM) − 5% 600 800 600 800 mA
IOUT(MAX) Short circuit current RL = 0 (Steady State)(3) 1000 1000 mA
en Output noise voltage (RMS) BW = 100 Hz to 100 kHz, COUT = 10 µF, CBYPASS = .01 µF, VOUT = 2.5 V 18 18 µV(RMS)
ΔVOUT/ΔVIN Ripple Rejection f = 1 kHz, COUT = 10 µF 60 60 dB
ΔVOUT/ΔTD Output voltage temperature coefficient See(2), –40°C ≤ TJ ≤ 125°C 20 20 ppm/°C
SHUTDOWN INPUT
VSD SD Input voltage VH = Output ON 1.4 1.4 V
VH = Output ON, –40°C ≤ TJ ≤ 125°C 1.6 1.6
VL = Output OFF 0.5 0.5
VL = Output OFF, IIN ≤ 2 µA, –40°C ≤ TJ ≤ 125°C 0.18 0.18
ISD SD Input current VSD = 0 0.001 0.001 µA
VSD = 0, –40°C ≤ TJ ≤ 125°C −1 −1
VSD = 5 V 5 5
VSD = 5 V, –40°C ≤ TJ ≤ 125°C 15 15
ERROR COMPARATOR
IOH Output “HIGH” leakage VOH = 16 V 0.001 1 0.001 1 µA
VOH = 16 V, –40°C ≤ TJ ≤ 125°C 0.001 2 0.001 2
VOL Output “LOW” voltage VIN = VOUT(NOM) − 0.5 V, IOUT(COMP) = 150 µA 150 220 150 220 mV
VIN = VOUT(NOM) − 0.5 V, IOUT(COMP) = 150 µA, –40°C ≤ TJ ≤ 125°C 150 350 150 350
VTHR(MAX) Upper threshold voltage −6 −4.8 −3.5 −6 −4.8 −3.5 %VOUT
–40°C ≤ TJ ≤ 125°C −8.3 −4.8 −2.5 −8.3 −4.8 −2.5
VTHR(MIN) Lower threshold voltage −8.9 −6.6 −4.9 −8.9 −6.6 −4.9 %VOUT
–40°C ≤ TJ ≤ 125°C −13 −6.6 −3 −13 −6.6 −3
HYST Hysteresis 2
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate TI’s Average Outgoing Quality Level (AOQL).
(2) Temperature coefficient is defined as the maximum (worst-case) change divided by the total temperature range.

6.6 Typical Characteristics

Unless otherwise specified: TA = 25°C, COUT = 10 µF, CIN = 2.2 µF, SD is tied to VIN, VIN = VO(NOM) + 1 V, IL = 1 mA,
VOUT = 1.8 V.
LP2989LV 10135707.png
Figure 1. IGND vs Shutdown
LP2989LV 10135709.png
Figure 3. IGND vs Shutdown
LP2989LV 10135722.png
Figure 5. Ground Pin Current vs Load Current
LP2989LV 10135732.png
Figure 7. Short-Circuit Current vs Temperature
LP2989LV 10135735.png
Figure 9. Short-Circuit Current
LP2989LV 10135755.gif
Figure 11. VOUT vs Junction Temperature (TJ)
LP2989LV 10135708.png
Figure 2. IGND vs Shutdown
LP2989LV 10135710.png
Figure 4. IGND vs Shutdown
LP2989LV 10135723.png
Figure 6. GND Pin Current vs Temperature and Load
LP2989LV 10135734.png
Figure 8. Short-Circuit Current
LP2989LV 10135739.png
Figure 10. Minimum VIN vs Load Current