SNVS056J May   2000  – June 2015 LP3961 , LP3964

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Short-Circuit Protection
      2. 7.3.2 ERROR Flag Operation
      3. 7.3.3 SENSE Pin
      4. 7.3.4 Dropout Voltage
      5. 7.3.5 Reverse Current Path
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VOUT(TARGET) + 0.35 V ≤ VIN ≤ 7 V
      2. 7.4.2 Operation With Shutdown (SD) Pin Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Capacitors
          1. 8.2.2.1.1 Input Capacitor
          2. 8.2.2.1.2 Output Capacitor
        2. 8.2.2.2 Selecting a Capacitor
        3. 8.2.2.3 Capacitor Characteristics
          1. 8.2.2.3.1 Ceramic
          2. 8.2.2.3.2 Tantalum
          3. 8.2.2.3.3 Aluminum
        4. 8.2.2.4 RFI and EMI Susceptibility
        5. 8.2.2.5 Output Adjustment
        6. 8.2.2.6 Turnon Characteristics for Output Voltages Programmed to 2.0 V or Below
        7. 8.2.2.7 Output Noise
        8. 8.2.2.8 Shutdown Operation
        9. 8.2.2.9 Maximum Output Current Capability
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Heatsinking TO-220 Packages
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

10 Layout

10.1 Layout Guidelines

Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops. The input and output capacitors must be directly connected to the IN, OUT, and GND pins of the LP396x using traces which do not have other currents flowing in them (Kelvin connect).

The best way to do this is to lay out CIN and COUT near the device with short traces to the IN, OUT, and GND pins. The regulator ground pin should be connected to the external circuit ground so that the regulator and its capacitors have a single-point ground.

It should be noted that stability problems have been seen in applications where vias to an internal ground plane were used at the ground points of the LP396x IC and the input and output capacitors. This was caused by varying ground potentials at these nodes resulting from current flowing through the ground plane. Using a single-point ground technique for the regulator and its capacitors fixed the problem.

Because high current flows through the traces going into the IN pin and coming from the OUT pin, Kelvin connect the capacitor leads to these pins so there is no voltage drop in series with the input and output capacitors.

10.2 Layout Example

LP3961 LP3964 LP3961_layout.gifFigure 26. LP3961 TO-263 Package Typical Layout
LP3961 LP3964 LP3964_layout.gifFigure 27. LP3964 TO-263 Package Typical Layout

10.3 Heatsinking TO-220 Packages

The thermal resistance of a TO-220 package can be reduced by attaching it to a heatsink or a copper plane on a PC board.

The heatsink to be used in the application should have a heatsink-to-ambient thermal resistance,

Equation 7. RθHA ≤ RθJA − RθCH − RθJC

In this equation, RθCH is the thermal resistance from the junction to the surface of the heatsink and RθJC is the thermal resistance from the junction to the surface of the case.