SNVS693E September 2011 – September 2014 LP8552
PRODUCTION DATA.
MIN | MAX | UNIT | ||
---|---|---|---|---|
VIN | –0.3 | 24 | V | |
VLDO | –0.3 | 6 | ||
Voltage on logic pins (VSYNC, PWM, EN, SCLK, SDA) | –0.3 | 6 | ||
Voltage on logic pin (FAULT) | –0.3 | VVDDIO + 0.3 | ||
Voltage on analog pins (FILTER, VDDIO, ISET, FSET) | –0.3 | 6 | ||
V (OUT1...OUT6, SW, FB) | –0.3 | 44 | ||
Continuous power dissipation (3) | Internally Limited | |||
Junction temperature (TJ-MAX) | 125 | °C | ||
Maximum lead temperature (soldering) | See (4) |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Tstg | Storage temperature range | –65 | 150 | °C | |
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | -2 | 2 | kV |
Charged device model (CDM), per JEDEC spec. JESD22-C101, all pins(2) | –200 | 200 | V | ||
Machine model | –1 | 1 | kV |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VIN (Figure 27) | Input voltage | 5.5 | 22 | V | |
VIN + VLDO (Figure 31) | 4.5 | 5.5 | |||
VDDIO | 1.65 | 5 | |||
V(OUT1...OUT6, SW, FB) | 0 | 40 | |||
TJ | Junction temperature | –30 | 125 | °C | |
TA(3) | Ambient temperature | –30 | 85 |
THERMAL METRIC(1) | DSBGA | UNIT | |
---|---|---|---|
25 PINS | |||
RθJA | Junction-to-ambient thermal resistance (2) | 40 - 73 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
IIN | Standby supply current | Internal LDO disabled EN=L and PWM=L |
1 (4) | μA | ||
Normal mode supply current | LDO enabled, boost enabled, no current going through LED outputs 5-MHz PLL Clock |
3 | mA | |||
10-MHz PLL Clock | 3.7 | |||||
20-MHz PLL Clock | 4.7 | |||||
40-MHz PLL Clock | 6.7 | |||||
fOSC | Internal oscillator frequency accuracy | –4% –7% (4) |
4% 7%(4) |
|||
VLDO | Internal LDO voltage | 4.5 (4) | 5 | 5.5 (4) | V | |
ILDO | Internal LDO external loading | 5 | mA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
RDSON | Switch ON resistance | ISW = 0.5 A | 0.12 | Ω | ||
VMAX | Boost maximum output voltage | 40 | V | |||
ILOAD | Maximum continuous load current | 9 V ≤ VBATT, VOUT = 35 V | 450 | mA | ||
6 V ≤ VBATT, VOUT = 35 V | 300 | |||||
3 V ≤ VBATT, VOUT = 25 V | 180 | |||||
VOUT/VIN | Conversion ratio | fSW = 1.25 MHz | 10 | |||
fSW | Switching frequency | BOOST_FREQ = 00 BOOST_FREQ = 01 BOOST_FREQ = 10 BOOST_FREQ = 11 |
156 312 625 1250 |
kHz | ||
VOV | Overvoltage protection voltage | VBOOST + 1.6V | V | |||
tPULSE | Switch pulse minimum width | no load | 50 | ns | ||
tSTARTUP | Start-up time | Note (2) | 6 | ms | ||
IMAX | SW pin current limit | BOOST_IMAX = 0 BOOST_IMAX = 1 |
1.4 2.5 |
A |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ILEAKAGE | Leakage current | Outputs OUT1 to OUT6, VOUT = 40 V | 0.1 | 1 | μA | |
IMAX | Maximum source current OUT1 to OUT6 | EN_I_RES = 0, CURRENT[7:0] = FFh | 30 | mA | ||
EN_I_RES = 1, CURRENT[7:0] = FFh | 50 | |||||
IOUT | Output current accuracy (2) | Output current set to 23 mA, EN_I_RES = 1 | –3% -4%(3) |
3% 4%(3) |
||
IMATCH | Matching(2) | Output current set to 23 mA, EN_I_RES = 1 | 0.5% | |||
PWMRES | PWM output resolution (4) | fLED = 5 kHz, fPLL = 5 MHz | 10 | bits | ||
fLED = 10 kHz, fPLL = 5 MHz | 9 | |||||
fLED = 20 kHz, fPLL = 5 MHz | 8 | |||||
fLED = 5 kHz, fPLL = 40 MHz | 13 | |||||
fLED = 10 kHz, fPLL = 40 MHz | 12 | |||||
fLED = 20 kHz, fPLL = 40 MHz | 11 | |||||
fLED | LED switching frequency(4) | PWM_FREQ[4:0] = 00000b PLL clock 5 MHz |
600 | Hz | ||
PWM_FREQ[4:0] = 11111b PLL clock 5 MHz |
19.2k | |||||
VSAT | Saturation voltage(5) | Output current set to 20 mA | 105 | 220(3) | mV | |
Output current set to 30 mA | 160 | 290(3) |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fPWM | PWM frequency range | 0.1 | 25 | kHz | ||
tMIN_ON | Minimum pulse ON time | 1 | μs | |||
tMIN_OFF | Minimum pulse OFF time | 1 | ||||
tSTARTUP | Turnon delay from standby to backlight on | PWM input active, EN pin rise from low to high | 6 | ms | ||
TSTBY | Turn off delay | PWM input low time for turn off, slope disabled | 50 | ms | ||
PWMRES | PWM input resolution | fIN < 9 kHz fIN < 4.5 kHz fIN < 2.2 kHz fIN < 1.1 kHz |
10 11 12 13 |
bits |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VUVLO | VIN UVLO threshold voltage | UVLO[1:0] = 00 | Disabled | V | ||
UVLO[1:0] = 01, falling | 2.55 | 2.70 | 2.94 | |||
UVLO[1:0] = 01, rising | 2.62 | 2.76 | 3.00 | |||
UVLO[1:0] = 10, falling | 5.11 | 5.40 | 5.68 | |||
UVLO[1:0] = 10, rising | 5.38 | 5.70 | 5.98 | |||
UVLO[1:0] = 11, falling | 7.75 | 8.10 | 8.45 | |||
UVLO[1:0] = 11, rising | 8.36 | 8.73 | 9.20 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
LOGIC INPUT EN | ||||||
VIL | Input low level | 0.4(1) | V | |||
VIH | Input high level | 1.2(1) | V | |||
II | Input current | -1(1) | 1(1) | μA | ||
LOGIC INPUT VSYNC | ||||||
VIL | Input low level | 0.4(1) | V | |||
VIH | Input high level | 2.2(1) | V | |||
II | Input current | –1(1) | 1(1) | μA | ||
fVSYNC | Frequency range | 58 | 60 | 55000 | Hz | |
LOGIC INPUT PWM | ||||||
VIL | Input low level | 0.2xVDDIO(1) | V | |||
VIH | Input high level | 0.8xVDDIO(1) | V | |||
II | Input current | –1(1) | 1(1) | μA | ||
LOGIC INPUTS SCL, SDA | ||||||
VIL | Input low level | 0.2xVDDIO(1) | V | |||
VIH | Input high level | 0.8xVDDIO(1) | V | |||
II | Input current | –1(1) | 1(1) | μA | ||
LOGIC OUTPUTS SDA, FAULT | ||||||
VOL | Output low level | IOUT = 3 mA (pull-up current) | 0.3 | 0.5(1) | V | |
IL | Output leakage current | VOUT = 2.8 V | –1(1) | 1(1) | μA |
MIN | MAX | UNIT | ||
---|---|---|---|---|
fCLK | Clock frequency | 400 | kHz | |
1 | Hold time (repeated) START condition | 0.6 | μs | |
2 | Clock low time | 1.3 | μs | |
3 | Clock high time | 600 | ns | |
4 | Setup time for a repeated START condition | 600 | ns | |
5 | Data hold time | 50 | ns | |
6 | Data setup time | 100 | ns | |
7 | Rise time of SDA and SCL | 20+0.1Cb | 300 | ns |
8 | Fall time of SDA and SCL | 15+0.1Cb | 300 | ns |
9 | Setup time for STOP condition | 600 | ns | |
10 | Bus free time between a STOP and a START condition | 1.3 | μs | |
Cb | Capacitive load parameter for each bus line Load of 1 pF corresponds to 1 ns. |
10 | 200 | ns |
fLED = 9.6 kHz |
fLED = 9.6 kHz | L1 = 15 µH |