JAJSST7 January   2024 MCF8315C-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings Auto
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Output Stage
      2. 6.3.2  Device Interface
        1. 6.3.2.1 Interface - Control and Monitoring
        2. 6.3.2.2 I2C Interface
      3. 6.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 6.3.3.1 Buck in Inductor Mode
        2. 6.3.3.2 Buck in Resistor mode
        3. 6.3.3.3 Buck Regulator with External LDO
        4. 6.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 6.3.3.5 Mixed Mode Buck Operation and Control
        6. 6.3.3.6 Buck Under Voltage Protection
        7. 6.3.3.7 Buck Over Current Protection
      4. 6.3.4  AVDD Linear Voltage Regulator
      5. 6.3.5  Charge Pump
      6. 6.3.6  Slew Rate Control
      7. 6.3.7  Cross Conduction (Dead Time)
      8. 6.3.8  Motor Control Input Sources
        1. 6.3.8.1 Analog Mode Motor Control
        2. 6.3.8.2 PWM Mode Motor Control
        3. 6.3.8.3 I2C based Motor Control
        4. 6.3.8.4 Frequency Mode Motor Control
        5. 6.3.8.5 Speed Profiles
          1. 6.3.8.5.1 Linear Reference Profiles
          2. 6.3.8.5.2 Staircase Reference Profiles
          3. 6.3.8.5.3 Forward-Reverse Reference Profiles
      9. 6.3.9  Starting the Motor Under Different Initial Conditions
        1. 6.3.9.1 Case 1 – Motor is Stationary
        2. 6.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 6.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 6.3.10 Motor Start Sequence (MSS)
        1. 6.3.10.1 Initial Speed Detect (ISD)
        2. 6.3.10.2 Motor Resynchronization
        3. 6.3.10.3 Reverse Drive
          1. 6.3.10.3.1 Reverse Drive Tuning
      11. 6.3.11 Motor Start-up
        1. 6.3.11.1 Align
        2. 6.3.11.2 Double Align
        3. 6.3.11.3 Initial Position Detection (IPD)
          1. 6.3.11.3.1 IPD Operation
          2. 6.3.11.3.2 IPD Release Mode
          3. 6.3.11.3.3 IPD Advance Angle
        4. 6.3.11.4 Slow First Cycle Start-up
        5. 6.3.11.5 Open loop
        6. 6.3.11.6 Transition from Open to Closed Loop
      12. 6.3.12 Closed Loop Operation
        1. 6.3.12.1 Closed Loop Acceleration/Deceleration Slew Rate
        2. 6.3.12.2 Speed PI Control
        3. 6.3.12.3 Current PI Control
        4. 6.3.12.4 Torque Mode
        5. 6.3.12.5 Overmodulation
      13. 6.3.13 Motor Parameters
        1. 6.3.13.1 Motor Resistance
        2. 6.3.13.2 Motor Inductance
        3. 6.3.13.3 Motor Back-EMF constant
      14. 6.3.14 Motor Parameter Extraction Tool (MPET)
      15. 6.3.15 Anti-Voltage Surge (AVS)
      16. 6.3.16 Active Braking
      17. 6.3.17 Output PWM Switching Frequency
      18. 6.3.18 PWM Modulation Schemes
      19. 6.3.19 Dead Time Compensation
      20. 6.3.20 Motor Stop Options
        1. 6.3.20.1 Coast (Hi-Z) Mode
        2. 6.3.20.2 Low-Side Braking
        3. 6.3.20.3 Active Spin-Down
      21. 6.3.21 FG Configuration
        1. 6.3.21.1 FG Output Frequency
        2. 6.3.21.2 FG during open loop
        3. 6.3.21.3 FG during idle and fault
      22. 6.3.22 DC Bus Current Limit
      23. 6.3.23 Protections
        1. 6.3.23.1  VM Supply Undervoltage Lockout
        2. 6.3.23.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 6.3.23.3  BUCK Under Voltage Lockout (BUCK_UV)
        4. 6.3.23.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 6.3.23.5  Overvoltage Protection (OVP)
        6. 6.3.23.6  Overcurrent Protection (OCP)
          1. 6.3.23.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 6.3.23.6.2 OCP Automatic Retry (OCP_MODE = 01b)
        7. 6.3.23.7  Buck Overcurrent Protection
        8. 6.3.23.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 6.3.23.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xxb)
          2. 6.3.23.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 01xxb)
          3. 6.3.23.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 1000b)
          4. 6.3.23.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE= 1xx1b)
        9. 6.3.23.9  Motor Lock (MTR_LCK)
          1. 6.3.23.9.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 6.3.23.9.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 6.3.23.9.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 6.3.23.9.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        10. 6.3.23.10 Motor Lock Detection
          1. 6.3.23.10.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 6.3.23.10.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 6.3.23.10.3 Lock3: No-Motor Fault (NO_MTR)
        11. 6.3.23.11 Minimum VM (undervoltage) Protection
        12. 6.3.23.12 Maximum VM (overvoltage) Protection
        13. 6.3.23.13 MPET Faults
        14. 6.3.23.14 IPD Faults
        15. 6.3.23.15 Thermal Warning (OTW)
        16. 6.3.23.16 Thermal Shutdown (TSD)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Functional Modes
        1. 6.4.1.1 Sleep Mode
        2. 6.4.1.2 Standby Mode
        3. 6.4.1.3 Fault Reset (CLR_FLT)
    5. 6.5 External Interface
      1. 6.5.1 DRVOFF Functionality
      2. 6.5.2 DAC output(s)
      3. 6.5.3 Current Sense Output
      4. 6.5.4 Oscillator Source
        1. 6.5.4.1 External Clock Source
      5. 6.5.5 External Watchdog
    6. 6.6 EEPROM access and I2C interface
      1. 6.6.1 EEPROM Access
        1. 6.6.1.1 EEPROM Write
        2. 6.6.1.2 EEPROM Read
        3. 6.6.1.3 EEPROM Security
      2. 6.6.2 I2C Serial Interface
        1. 6.6.2.1 I2C Data Word
        2. 6.6.2.2 I2C Write Transaction
        3. 6.6.2.3 I2C Read Transaction
        4. 6.6.2.4 I2C Communication Protocol Packet Examples
        5. 6.6.2.5 I2C Clock Stretching
        6. 6.6.2.6 CRC Byte Calculation
    7. 6.7 EEPROM (Non-Volatile) Register Map
      1. 6.7.1 Algorithm_Configuration Registers
      2. 6.7.2 Fault_Configuration Registers
      3. 6.7.3 Hardware_Configuration Registers
      4. 6.7.4 Internal_Algorithm_Configuration Registers
    8. 6.8 RAM (Volatile) Register Map
      1. 6.8.1 Fault_Status Registers
      2. 6.8.2 System_Status Registers
      3. 6.8.3 Device_Control Registers
      4. 6.8.4 Algorithm_Control Registers
      5. 6.8.5 Algorithm_Variables Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Application Curves
        1. 7.2.1.1 Motor startup
        2. 7.2.1.2 MPET
        3. 7.2.1.3 Dead time compensation
        4. 7.2.1.4 Auto handoff
        5. 7.2.1.5 Anti voltage surge (AVS)
        6. 7.2.1.6 Real time variable tracking using DACOUT
  9. 8 Power Supply Recommendations
    1. 8.1 Bulk Capacitance
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Thermal Considerations
      1. 9.2.1 Power Dissipation
  11. 10Device and Documentation Support
    1. 10.1 サポート・リソース
    2. 10.2 Trademarks
    3. 10.3 静電気放電に関する注意事項
    4. 10.4 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

TJ = –40°C to +150°C, VVM = 4.5 to 35V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER SUPPLIES
IVMQVM sleep mode currentVVM > 6 V, VSPEED = 0, TA = 25 °C35µA
VSPEED = 0, TA = 125 °C3.57µA
IVMSVM standby mode currentVVM ≥ 12 V, Standby Mode, DRVOFF = High, TA = 25 °C, LBK = 47 µH, CBK = 22 µF 816mA
VVM ≥ 12 V, Standby Mode, DRVOFF = High, TA = 25 °C, RBK = 22 Ω, CBK = 22 µF2529mA
VVM ≥ 12 V, Standby Mode, DRVOFF = High, LBK = 47 µH, CBK = 22 µF 816.5mA
VVM ≥ 12 V, Standby Mode, DRVOFF = High, RBK = 22 Ω, CBK = 22 µF2529mA
IVMVM operating mode currentVVM ≥ 12 V, VSPEED > VEX_SL, PWM_FREQ_OUT = 0011b (25 kHz), TA = 25 °C, LBK = 47 µH, CBK = 22 µF, No Motor Connected1118mA
VVM ≥ 12 V, VSPEED > VEX_SL, PWM_FREQ_OUT = 0011b (25 kHz), TA = 25 °C, RBK = 22 Ω, CBK = 22 µF, No Motor Connected2731.5mA
VVM ≥ 12 V, VSPEED > VEX_SL, PWM_FREQ_OUT = 0011b (25 kHz), LBK = 47 µH, CBK = 22 µF, No Motor Connected1118mA
VVM ≥ 12 V, VSPEED > VEX_SL, PWM_FREQ_OUT = 0011b (25 kHz), RBK = 22 Ω, CBK = 22 µF, No Motor Connected2832mA
VAVDDAnalog regulator voltage0 mA ≤ IAVDD ≤ 20 mA3.1253.33.465V
IAVDDExternal analog regulator load20mA
VDVDDDigital regulator voltage1.41.551.65V
VVCPCharge pump regulator voltageVCP with respect to VM4.04.75.5V
BUCK REGULATOR
VBKBuck regulator average voltage
(LBK = 47 µH, CBK = 22 µF)
 		VVM > 6 V, 0 mA ≤ IBK ≤ 170 mA, BUCK_SEL = 00b3.13.33.5V
VVM > 6 V, 0 mA ≤ IBK ≤ 170 mA, BUCK_SEL = 01b4.65.05.4V
VVM > 6 V, 0 mA ≤ IBK ≤ 170 mA, BUCK_SEL = 10b3.74.04.3V
VVM > 6.7 V, 0 mA ≤ IBK ≤ 170 mA, BUCK_SEL = 11b5.25.75.8V
VVM < 6.0 V (BUCK_SEL = 00b, 01b, 10b, 11b), 0 mA ≤ IBK ≤ 170 mAVVM–IBK*(RLBK+2) 1V
VBKBuck regulator average voltage
(LBK = 22 µH, CBK = 22 µF)
 		VVM > 6 V, 0 mA ≤ IBK ≤ 20 mA, BUCK_SEL = 00b3.13.33.5V
VVM > 6 V, 0 mA ≤ IBK ≤ 20 mA, BUCK_SEL = 01b4.65.05.4V
VVM > 6 V, 0 mA ≤ IBK ≤ 20 mA, BUCK_SEL = 10b3.74.04.3V
VVM > 6.7 V, 0 mA ≤ IBK ≤ 20 mA, BUCK_SEL = 11b5.25.75.8V
VVM < 6.0 V (BUCK_SEL = 00b, 01b, 10b, 11b), 0 mA ≤ IBK ≤ 20 mAVVM–IBK*(RLBK+2)1V
VBKBuck regulator average voltage
(RBK = 22 Ω, CBK = 22 µF)
 		VVM > 6 V, 0 mA ≤ IBK ≤ 10 mA, BUCK_SEL = 00b3.13.33.5V
VVM > 6 V, 0 mA ≤ IBK ≤ 10 mA, BUCK_SEL = 01b4.65.05.4V
VVM > 6 V, 0 mA ≤ IBK ≤ 10 mA, BUCK_SEL = 10b3.74.04.3V
VVM > 6.7 V, 0 mA ≤ IBK ≤ 10 mA, BUCK_SEL = 11b5.25.75.8V
VVM < 6.0 V (BUCK_SEL = 00b, 01b, 10b, 11b), 0 mA ≤ IBK ≤ 10 mAVVM–IBK*(RBK+2)V
VBK_RIPBuck regulator ripple voltageVVM > 6 V, 0 mA ≤ IBK ≤ 170 mA, Buck regulator with inductor, LBK = 47 µH, CBK = 22 µF–100100mV
VVM > 6 V, 0 mA ≤ IBK ≤ 20 mA, Buck regulator with inductor, LBK = 22 µH, CBK = 22 µF–100100mV
VVM > 6 V, 0 mA ≤ IBK ≤ 10 mA, Buck regulator with resistor; RBK = 22 Ω, CBK = 22 µF–100100mV
IBKExternal buck regulator loadLBK = 47 µH, CBK = 22 µF, BUCK_PS_DIS = 1b170mA
LBK = 47 µH, CBK = 22 µF, BUCK_PS_DIS = 0b170 – IAVDDmA
LBK = 22 µH, CBK = 22 µF, BUCK_PS_DIS = 1b20mA
LBK = 22 µH, CBK = 22 µF, BUCK_PS_DIS = 0b20 – IAVDDmA
RBK = 22 Ω, CBK = 22 µF, BUCK_PS_DIS = 1b10mA
RBK = 22 Ω, CBK = 22 µF, BUCK_PS_DIS = 0b10 – IAVDDmA
fSW_BKBuck regulator switching frequencyRegulation Mode20535kHz
Linear Mode20535kHz
VBK_UVBuck regulator undervoltage lockout
 		VBK rising, BUCK_SEL = 00b2.72.82.95V
VBK falling, BUCK_SEL = 00b2.52.62.7V
VBK rising, BUCK_SEL = 01b4.34.44.55V
VBK falling, BUCK_SEL = 01b4.14.24.37V
VBK rising, BUCK_SEL = 10b2.72.82.95V
VBK falling, BUCK_SEL = 10b2.52.62.7V
VBK rising, BUCK_SEL = 11b4.34.44.55V
VBK falling, BUCK_SEL = 11b4.14.24.36V
VBK_UV_HYSBuck regulator undervoltage lockout hysteresisRising to falling threshold, BUCK_SEL = 00b90200400mV
Rising to falling threshold, BUCK_SEL = 01b70200400mV
Rising to falling threshold, BUCK_SEL = 10b90200400mV
Rising to falling threshold, BUCK_SEL =11b70200400mV
IBK_CLBuck regulator current limit threshold
 		BUCK_CL = 0b360600910mA
BUCK_CL = 1b80150250mA
IBK_OCPBuck regulator over current protection trip point234A
tBK_RETRYOver current protection retry time0.711.3ms
DRIVER OUTPUTS
RDS(ON) (RGF)Total MOSFET on resistance (High-side + Low-side)VVM > 6 V, IOUT = 1 A, TA = 25°C240260mΩ
VVM < 6 V, IOUT = 1 A, TA = 25°C250270mΩ
VVM > 6 V, IOUT = 1 A, TJ = 150 °C360400mΩ
VVM < 6 V, IOUT = 1 A, TJ = 150 °C370415mΩ
RDS(ON) (RRY)Total MOSFET on resistance (High-side + Low-side)VVM > 6 V, IOUT = 1 A, TA = 25°C250270mΩ
VVM < 6 V, IOUT = 1 A, TA = 25°C260280mΩ
VVM > 6 V, IOUT = 1 A, TJ = 150 °C375415mΩ
VVM < 6 V, IOUT = 1 A, TJ = 150 °C385425mΩ
RDS(ON) (PWP)Total MOSFET on resistance (High-side + Low-side)VVM > 6 V, IOUT = 1 A, TA = 25°C265280mΩ
VVM < 6 V, IOUT = 1 A, TA = 25°C275290mΩ
VVM > 6 V, IOUT = 1 A, TJ = 150 °C390430mΩ
VVM < 6 V, IOUT = 1 A, TJ = 150 °C400440mΩ
SRPhase pin slew rate switching low to high (Rising from 20 % to 80 %)VVM = 24 V, SLEW_RATE = 10b80125210V/µs
VVM = 24 V, SLEW_RATE = 11b130200315V/µs
SRPhase pin slew rate switching high to low (Falling from 80 % to 20 %)VVM = 24 V, SLEW_RATE = 10b80125235V/µs
VVM = 24 V, SLEW_RATE = 11b110200345V/µs
tDEADOutput dead time (high to low / low to high)VVM = 24 V, SR = 125 V/µs650850ns
VVM = 24 V, SR = 200 V/µs500550ns
SPEED INPUT - PWM MODE
ƒPWMPWM input frequency0.01100kHz
ResPWMPWM input resolutionfPWM = 0.01 to 0.35 kHz111213bits
fPWM = 0.35 to 2 kHz111314bits
fPWM = 2 to 3.5 kHz1111.512bits
fPWM = 3.5 to 7 kHz121313.5bits
fPWM = 7 to 14 kHz111212.5bits
fPWM = 14 to 29.2 kHz 1011.512bits
fPWM = 29.3 to 60 kHz910.511bits
fPWM = 60 to 100 kHz8910bits
SPEED INPUT - ANALOG MODE
VANA_FSAnalog full-speed voltage2.9533.05V
VANA_RESAnalog voltage resolution732μV
SPEED INPUT - FREQUENCY MODE
ƒPWM_FREQPWM input frequency range Duty cycle = 50%332767Hz
SLEEP MODE
VEN_SLAnalog voltage to enter sleep modeSPEED_MODE = 00b (Analog mode)40mV
VEX_SLAnalog voltage to exit sleep modeSPEED_MODE = 00b (Analog mode)2.2V
tDET_ANATime needed to detect wake up signal on SPEED pin SPEED_MODE = 00b (Analog mode)
VSPEED > VEX_SL		0.511.5μs
tWAKEWakeup time from sleep modeVSPEED > VEX_SL to DVDD voltage available, SPEED_MODE = 00b (Analog mode)35ms
tEX_SL_DR_ANATime taken to drive motor after exiting from sleep stateSPEED_MODE = 00b (analog mode), DVDD voltage available to first output PWM pulse, ISD detection disabled30ms
tDET_PWMTime needed to detect wake up signal on SPEED pin SPEED_MODE = 01b (PWM mode) or 11b (Frequency mode), VSPEED > VIH0.511.5μs
tWAKE_PWMWakeup time from sleep modeVSPEED > VIH to DVDD voltage available, SPEED_MODE = 01b (PWM mode) or 11b (Frequency mode)35ms
tEX_SL_DR_PWMTime taken to drive motor after wakeup from sleep stateSPEED_MODE = 01b (PWM mode) or 11b (Frequency mode), DVDD voltage available to first output PWM pulse, ISD detection disabled30ms
tDET_SL_ANATime needed to detect sleep command, analog modeSPEED_MODE = 00b (Analog mode) VSPEED < VEN_SL, SLEEP_ENTRY_TIME = 00b0.0350.050.065ms
SPEED_MODE = 00b (Analog mode) VSPEED < VEN_SL, SLEEP_ENTRY_TIME= 01b0.140.20.26ms
SPEED_MODE = 00b (Analog mode) VSPEED < VEN_SL, SLEEP_ENTRY_TIME = 10b142026ms
SPEED_MODE = 00b (Analog mode) VSPEED < VEN_SL, SLEEP_ENTRY_TIME= 11b140200260ms
tDET_SL_PWMTime needed to detect sleep command, PWM or frequency modeSPEED_MODE = 01b (PWM mode) or 11b (Frequency mode),
VSPEED < VIL, SLEEP_ENTRY_TIME = 00b		0.0350.050.065ms
SPEED_MODE = 01b (PWM mode) or 11b (Frequency mode),
VSPEED < VIL, SLEEP_ENTRY_TIME = 01b		0.140.20.26ms
SPEED_MODE = 01b (PWM mode) or 11b (Frequency mode),
VSPEED < VIL, SLEEP_ENTRY_TIME  = 10b		142026ms
SPEED_MODE = 01b (PWM mode) or 11b (Frequency mode),
VSPEED < VIL, SLEEP_ENTRY_TIME = 11b		140200260ms
tEN_SLTime needed to stop driving motor after detecting sleep commandVSPEED < VEN_SL (Analog mode) or VSPEED < VIL (PWM mode or Frequency mode) or VSPEED < VIL and DIGITAL_SPEED_CTRL = 0 (I2C mode)12ms
STANDBY MODE
tEX_SB_DR_ANATime taken to drive motor after exiting standby mode, analog modeSPEED_MODE = 00b (Analog mode), VSPEED > VEX_SB, ISD detection disabled6ms
tEX_SB_DR_PWMTime taken to drive motor after exiting standby mode, PWM modeSPEED_MODE = 01b (PWM mode)
VSPEED > VIH, ISD detection disabled		6ms
tDET_SB_ANATime needed to detect standby mode, analog modeSPEED_MODE = 00b (Analog mode), VSPEED < VEN_SB0.512ms
tDET_SB_PWMTime needed to detect standby command, PWM/Freq modeSPEED_MODE = 01b (PWM mode) or SPEED_MODE = 11b (Freq mode),
VSPEED < VIL, SLEEP_ENTRY_TIME = 00b		0.0350.050.065ms
SPEED_MODE = 01b (PWM mode) or SPEED_MODE = 11b (Freq mode), VSPEED < VIL, SLEEP_ENTRY_TIME = 01b0.140.20.26ms
SPEED_MODE = 01b (PWM mode) or SPEED_MODE = 11b (Freq mode), VSPEED < VIL, SLEEP_ENTRY_TIME = 10b142026ms
SPEED_MODE = 01b (PWM mode) or SPEED_MODE = 11b (Freq mode),
VSPEED < VIL, SLEEP_ENTRY_TIME = 11b		140200260ms
tDET_SB_DIGTime needed to detect standby mode, I2C modeSPEED_MODE = 10b (I2C mode), DIGITAL_SPEED_CTRL = 0b12ms
tEN_SBTime needed to stop driving motor after detecting standby commandAll speed input modes12ms
LOGIC-LEVEL INPUTS (BRAKE, DIR, EXT_CLK, EXT_WD, SPEED)
VILInput logic low voltageAVDD = 3 to 3.6 V0.25*AVDDV
VIHInput logic high voltageAVDD = 3 to 3.6 V0.65*AVDDV
VHYSInput hysteresis50500800mV
IILInput logic low currentAVDD = 3 to 3.6 V-0.150.15µA
IIHInput logic high currentAVDD  = 3 to 3.6 V-0.30µA
RPD_SPEEDInput pulldown resistanceSPEED pin To GND0.611.4MΩ
OPEN-DRAIN OUTPUTS (nFAULT, FG)
VOLOutput logic low voltageIOD = -5 mA0.4V
IOZOutput logic high currentVOD = 3.3 V00.5µA
I2C Serial Interface
VI2C_LInput logic low voltage-0.50.3*AVDDV
VI2C_HInput logic high voltage0.7*AVDD5.5V
VI2C_HYSHysteresis 0.05*AVDDV
VI2C_OLOutput logic low voltageOpen-drain at 2mA sink current 00.4V
II2C_OLOutput logic low currentVI2C_OL = 0.6V6mA
II2C_ILInput current on SDA and SCL-102102µA
CiCapacitance for SDA and SCL10pF
tofOutput fall time from VI2C_H(min) to VI2C_L(max)Standard Mode2503ns
Fast Mode2503ns
tSPPulse width of spikes that must be suppressed by the input filterFast Mode0504ns
OSCILLATOR
fOSCREFExternal clock referenceEXT_CLK_CONFIG = 000b8kHz
EXT_CLK_CONFIG = 001b16kHz
EXT_CLK_CONFIG = 010b32kHz
EXT_CLK_CONFIG = 011b64kHz
EXT_CLK_CONFIG = 100b128kHz
EXT_CLK_CONFIG = 101b256kHz
EXT_CLK_CONFIG = 110b512kHz
EXT_CLK_CONFIG = 111b1024kHz
EEPROM
EEProgProgramming voltage1.351.51.65V
EERETRetentionTA = 25 ℃100Years
TJ = -40 to 150 ℃10Years
EEENDEnduranceTJ = -40 to 150 ℃1000Cycles
TJ = -40 to 85 ℃20000Cycles
PROTECTION CIRCUITS
VUVLOSupply under voltage lockout (UVLO)VM rising4.34.44.51V
VM falling4.14.24.32V
VUVLO_HYSSupply under voltage lockout hysteresisRising to falling threshold90200350mV
tUVLOSupply under voltage deglitch time357µs
VOVPSupply over voltage protection (OVP) thresholdSupply rising, OVP_EN = 1, OVP_SEL = 032.53435V
Supply falling, OVP_EN = 1, OVP_SEL = 031.83334.3V
Supply rising, OVP_EN = 1, OVP_SEL = 1202223V
Supply falling, OVP_EN = 1, OVP_SEL = 1192122V
VOVP_HYSSupply over voltage protection hysteresisRising to falling threshold, OVP_SEL = 10.911.15V
Rising to falling threshold, OVP_SEL = 00.70.80.9V
tOVPSupply over voltage deglitch time2.557µs
VCPUVCharge pump under voltage lockout (above VM)Supply rising2.252.52.75V
Supply falling2.22.42.6V
VCPUV_HYSCharge pump UVLO hysteresisRising to falling threshold65100150mV
VAVDD_UVAnalog regulator (AVDD) under voltage lockoutSupply rising2.72.853V
Supply falling2.482.652.8V
VAVDD_UV_HYSAnalog regulator under voltage lockout hysteresisRising to falling threshold180200240mV
IOCPOver current protection trip pointOCP_LVL = 0b5.5912A
OCP_LVL = 1b91318A
tOCPOver current protection deglitch timeOCP_DEG = 00b0.020.20.4µs
OCP_DEG = 01b0.20.61.2µs
OCP_DEG = 10b0.51.21.8µs
OCP_DEG = 11b0.91.62.5µs
tRETRYOver current protection retry time425500575ms
TOTWThermal warning temperatureDie temperature (TJ)135145155°C
TOTW_HYSThermal warning hysteresisDie temperature (TJ)152530°C
TTSD_BUCKThermal shutdown temperature (Buck)Die temperature (TJ)170180190°C
TTSD_BUCK_HYSThermal shutdown hysteresis (Buck)Die temperature (TJ)152530°C
TTSDThermal shutdown temperature (FET)Die temperature (TJ)165175185°C
TTSD_HYSThermal shutdown hysteresis (FET)Die temperature (TJ)152530°C
(1) RLBK is the resistance of the inductor LBK.
(2) If AVDD is switched off, I/O pins must not obstruct the SDA and SCL lines.
(3) The maximum tf for the SDA and SCL bus lines (300ns) is longer than the specified maximum tof for the output stages (250ns). This allows series protection resistors (Rs) to be connected between the SDA/SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.
(4) Input filters on the SDA and SCL inputs suppress noise spikes of less than 50ns.