JAJSCD6E August   2016  – June 2021 MSP430FR2000 , MSP430FR2100 , MSP430FR2110 , MSP430FR2111

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Connection of Unused Pins
    6. 7.6 Buffer Type
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Active Mode Supply Current Per MHz
    6. 8.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode LPM3, LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Typical Characteristics – LPM Supply Currents
    10. 8.10 Current Consumption Per Module
    11. 8.11 Thermal Resistance Characteristics
    12. 8.12 Timing and Switching Characteristics
      1. 8.12.1  Power Supply Sequencing
        1. 8.12.1.1 PMM, SVS and BOR
      2. 8.12.2  Reset Timing
        1. 8.12.2.1 Wake-up Times From Low-Power Modes and Reset
      3. 8.12.3  Clock Specifications
        1. 8.12.3.1 XT1 Crystal Oscillator (Low Frequency)
        2. 8.12.3.2 DCO FLL, Frequency
        3. 8.12.3.3 DCO Frequency
        4. 8.12.3.4 REFO
        5. 8.12.3.5 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        6. 8.12.3.6 Module Oscillator (MODOSC)
      4. 8.12.4  Digital I/Os
        1. 8.12.4.1 Digital Inputs
        2. 8.12.4.2 Digital Outputs
        3. 8.12.4.3 Digital I/O Typical Characteristics
      5. 8.12.5  VREF+ Built-in Reference
        1. 8.12.5.1 VREF+ Characteristics
      6. 8.12.6  Timer_B
        1. 8.12.6.1 Timer_B
      7. 8.12.7  eUSCI
        1. 8.12.7.1 eUSCI (UART Mode) Clock Frequency
        2. 8.12.7.2 eUSCI (UART Mode) Switching Characteristics
        3. 8.12.7.3 eUSCI (SPI Master Mode) Clock Frequency
        4. 8.12.7.4 eUSCI (SPI Master Mode) Switching Characteristics
        5. 8.12.7.5 eUSCI (SPI Slave Mode) Switching Characteristics
      8. 8.12.8  ADC
        1. 8.12.8.1 ADC, Power Supply and Input Range Conditions
        2. 8.12.8.2 ADC, 10-Bit Timing Parameters
        3. 8.12.8.3 ADC, 10-Bit Linearity Parameters
      9. 8.12.9  Enhanced Comparator (eCOMP)
        1. 8.12.9.1 eCOMP Characteristics
      10. 8.12.10 FRAM
        1. 8.12.10.1 FRAM Characteristics
      11. 8.12.11 Emulation and Debug
        1. 8.12.11.1 JTAG, Spy-Bi-Wire Interface
        2. 8.12.11.2 JTAG, 4-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Operating Modes
    4. 9.4  Interrupt Vector Addresses
    5. 9.5  Memory Organization
    6. 9.6  Bootloader (BSL)
    7. 9.7  JTAG Standard Interface
    8. 9.8  Spy-Bi-Wire Interface (SBW)
    9. 9.9  FRAM
    10. 9.10 Memory Protection
    11. 9.11 Peripherals
      1. 9.11.1  Power-Management Module (PMM) and On-Chip Reference Voltages
      2. 9.11.2  Clock System (CS) and Clock Distribution
      3. 9.11.3  General-Purpose Input/Output Port (I/O)
      4. 9.11.4  Watchdog Timer (WDT)
      5. 9.11.5  System Module (SYS)
      6. 9.11.6  Cyclic Redundancy Check (CRC)
      7. 9.11.7  Enhanced Universal Serial Communication Interface (eUSCI_A0)
      8. 9.11.8  Timers (Timer0_B3)
      9. 9.11.9  Backup Memory (BAKMEM)
      10. 9.11.10 Real-Time Clock (RTC) Counter
      11. 9.11.11 10-Bit Analog-to-Digital Converter (ADC)
      12. 9.11.12 eCOMP0
      13. 9.11.13 Embedded Emulation Module (EEM)
      14. 9.11.14 Peripheral File Map
      15. 9.11.15 Input/Output Diagrams
        1. 9.11.15.1 Port P1 Input/Output With Schmitt Trigger
        2. 9.11.15.2 Port P2 Input/Output With Schmitt Trigger
    12. 9.12 Device Descriptors (TLV)
    13. 9.13 Identification
      1. 9.13.1 Revision Identification
      2. 9.13.2 Device Identification
      3. 9.13.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2 External Oscillator
      3. 10.1.3 JTAG
      4. 10.1.4 Reset
      5. 10.1.5 Unused Pins
      6. 10.1.6 General Layout Recommendations
      7. 10.1.7 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC Peripheral
        1. 10.2.1.1 Partial Schematic
        2. 10.2.1.2 Design Requirements
        3. 10.2.1.3 Layout Guidelines
    3. 10.3 Typical Applications
  11. 11Device and Documentation Support
    1. 11.1 Getting Started
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.11.14 Peripheral File Map

#GUID-2BB747CA-D959-4555-859B-6E05603B0910/SLASE782520 lists the base address and the memory size of the registers for each peripheral.

Table 9-18 Peripherals Summary
MODULE NAMEBASE ADDRESSSIZE
Special Functions (see #GUID-2BB747CA-D959-4555-859B-6E05603B0910/SLASE784493)0100h0010h
PMM (see #GUID-2BB747CA-D959-4555-859B-6E05603B0910/SLASE78686)0120h0020h
SYS (see #GUID-2BB747CA-D959-4555-859B-6E05603B0910/SLASE783335)0140h0040h
CS (see #GUID-2BB747CA-D959-4555-859B-6E05603B0910/SLASE782719)0180h0020h
FRAM (see #GUID-2BB747CA-D959-4555-859B-6E05603B0910/SLASE786772)01A0h0010h
CRC (see #GUID-2BB747CA-D959-4555-859B-6E05603B0910/SLASE783519)01C0h0008h
WDT (see #GUID-2BB747CA-D959-4555-859B-6E05603B0910/SLASE782022)01CCh0002h
Port P1, P2 (see #GUID-2BB747CA-D959-4555-859B-6E05603B0910/SLASE788286)0200h0020h
Capacitive Touch I/O (see #GUID-2BB747CA-D959-4555-859B-6E05603B0910/SLASE781913)02E0h0010h
RTC (see #GUID-2BB747CA-D959-4555-859B-6E05603B0910/SLASE788224)0300h0010h
Timer0_B3 (see #GUID-2BB747CA-D959-4555-859B-6E05603B0910/SLASE789566)0380h0030h
eUSCI_A0 (see #GUID-2BB747CA-D959-4555-859B-6E05603B0910/SLASE78331)0500h0020h
Backup Memory (see #GUID-2BB747CA-D959-4555-859B-6E05603B0910/SLASE788654)0660h0020h
ADC(1) (see #GUID-2BB747CA-D959-4555-859B-6E05603B0910/SLASE784610)0700h0040h
eCOMP0 (see #GUID-2BB747CA-D959-4555-859B-6E05603B0910/SLASE786888)08E0h0020h
(1) The ADC is not available on the MSP430FR2000 device.
Table 9-19 Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTIONREGISTEROFFSET
SFR interrupt enableSFRIE100h
SFR interrupt flagSFRIFG102h
SFR reset pin controlSFRRPCR04h
Table 9-20 PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTIONREGISTEROFFSET
PMM control 0PMMCTL000h
PMM control 1PMMCTL102h
PMM control 2PMMCTL204h
PMM interrupt flagsPMMIFG0Ah
PM5 control 0PM5CTL010h
Table 9-21 SYS Registers (Base Address: 0140h)
REGISTER DESCRIPTIONREGISTEROFFSET
System controlSYSCTL00h
Bootloader configuration areaSYSBSLC02h
JTAG mailbox controlSYSJMBC06h
JTAG mailbox input 0SYSJMBI008h
JTAG mailbox input 1SYSJMBI10Ah
JTAG mailbox output 0SYSJMBO00Ch
JTAG mailbox output 1SYSJMBO10Eh
User NMI vector generatorSYSUNIV1Ah
System NMI vector generatorSYSSNIV1Ch
Reset vector generatorSYSRSTIV1Eh
System configuration 0SYSCFG020h
System configuration 1SYSCFG122h
System configuration 2SYSCFG224h
System configuration 3SYSCFG326h
Table 9-22 CS Registers (Base Address: 0180h)
REGISTER DESCRIPTIONREGISTEROFFSET
CS control 0CSCTL000h
CS control 1CSCTL102h
CS control 2CSCTL204h
CS control 3CSCTL306h
CS control 4CSCTL408h
CS control 5CSCTL50Ah
CS control 6CSCTL60Ch
CS control 7CSCTL70Eh
CS control 8CSCTL810h
Table 9-23 FRAM Registers (Base Address: 01A0h)
REGISTER DESCRIPTIONREGISTEROFFSET
FRAM control 0FRCTL000h
General control 0GCCTL004h
General control 1GCCTL106h
Table 9-24 CRC Registers (Base Address: 01C0h)
REGISTER DESCRIPTIONREGISTEROFFSET
CRC data inputCRC16DI00h
CRC data input reverse byteCRCDIRB02h
CRC initialization and resultCRCINIRES04h
CRC result reverse byteCRCRESR06h
Table 9-25 WDT Registers (Base Address: 01CCh)
REGISTER DESCRIPTIONREGISTEROFFSET
Watchdog timer controlWDTCTL00h
Table 9-26 Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTIONREGISTEROFFSET
Port P1 inputP1IN00h
Port P1 outputP1OUT02h
Port P1 directionP1DIR04h
Port P1 pulling enableP1REN06h
Port P1 selection 0P1SEL00Ah
Port P1 selection 1P1SEL10Ch
Port P1 interrupt vector wordP1IV0Eh
Port P1 complement selectionP1SELC16h
Port P1 interrupt edge selectP1IES18h
Port P1 interrupt enableP1IE1Ah
Port P1 interrupt flagP1IFG1Ch
Port P2 inputP2IN01h
Port P2 outputP2OUT03h
Port P2 directionP2DIR05h
Port P2 pulling enableP2REN07h
Port P2 selection 0P2SEL00Bh
Port P2 selection 1P2SEL10Dh
Port P2 complement selectionP2SELC17h
Port P2 interrupt vector wordP2IV1Eh
Port P2 interrupt edge selectP2IES19h
Port P2 interrupt enableP2IE1Bh
Port P2 interrupt flagP2IFG1Dh
Table 9-27 Capacitive Touch I/O Registers (Base Address: 02E0h)
REGISTER DESCRIPTIONREGISTEROFFSET
Capacitive Touch I/O 0 controlCAPIO0CTL0Eh
Table 9-28 RTC Registers (Base Address: 0300h)
REGISTER DESCRIPTIONREGISTEROFFSET
RTC controlRTCCTL00h
RTC interrupt vectorRTCIV04h
RTC moduloRTCMOD08h
RTC counterRTCCNT0Ch
Table 9-29 Timer0_B3 Registers (Base Address: 0380h)
REGISTER DESCRIPTIONREGISTEROFFSET
TB0 controlTB0CTL00h
Capture/compare control 0TB0CCTL002h
Capture/compare control 1TB0CCTL104h
Capture/compare control 2TB0CCTL206h
TB0 counterTB0R10h
Capture/compare 0TB0CCR012h
Capture/compare 1TB0CCR114h
Capture/compare 2TB0CCR216h
TB0 expansion 0TB0EX020h
TB0 interrupt vectorTB0IV2Eh
Table 9-30 eUSCI_A0 Registers (Base Address: 0500h)
REGISTER DESCRIPTIONREGISTEROFFSET
eUSCI_A control word 0UCA0CTLW000h
eUSCI_A control word 1UCA0CTLW102h
eUSCI_A control rate 0UCA0BR006h
eUSCI_A control rate 1UCA0BR107h
eUSCI_A modulation controlUCA0MCTLW08h
eUSCI_A statusUCA0STAT0Ah
eUSCI_A receive bufferUCA0RXBUF0Ch
eUSCI_A transmit bufferUCA0TXBUF0Eh
eUSCI_A LIN controlUCA0ABCTL10h
eUSCI_A IrDA transmit controllUCA0IRTCTL12h
eUSCI_A IrDA receive controlIUCA0IRRCTL13h
eUSCI_A interrupt enableUCA0IE1Ah
eUSCI_A interrupt flagsUCA0IFG1Ch
eUSCI_A interrupt vector wordUCA0IV1Eh
Table 9-31 Backup Memory Registers (Base Address: 0660h)
REGISTER DESCRIPTIONREGISTEROFFSET
Backup memory 0BAKMEM000h
Backup memory 1BAKMEM102h
Backup memory 2BAKMEM204h
Backup memory 3BAKMEM306h
Backup memory 4BAKMEM408h
Backup memory 5BAKMEM50Ah
Backup memory 6BAKMEM60Ch
Backup memory 7BAKMEM70Eh
Backup memory 8BAKMEM810h
Backup memory 9BAKMEM912h
Backup memory 10BAKMEM1014h
Backup memory 11BAKMEM1116h
Backup memory 12BAKMEM1218h
Backup memory 13BAKMEM131Ah
Backup memory 14BAKMEM141Ch
Backup memory 15BAKMEM151Eh
Table 9-32 ADC Registers (Base Address: 0700h)
REGISTER DESCRIPTIONREGISTEROFFSET
ADC control 0ADCCTL000h
ADC control 1ADCCTL102h
ADC control 2ADCCTL204h
ADC window comparator low thresholdADCLO06h
ADC window comparator high thresholdADCHI08h
ADC memory control 0ADCMCTL00Ah
ADC conversion memoryADCMEM012h
ADC interrupt enableADCIE1Ah
ADC interrupt flagsADCIFG1Ch
ADC interrupt vector wordADCIV1Eh
Table 9-33 eCOMP0 Registers (Base Address: 08E0h)
REGISTER DESCRIPTIONREGISTEROFFSET
Comparator control 0CPCTL000h
Comparator control 1CPCTL102h
Comparator interruptCPINT06h
Comparator interrupt vectorCPIV08h
Comparator built-in DAC controlCPDACCTL10h
Comparator built-in DAC dataCPDACDATA12h