JAJSFF4D May   2018  – December 2019 MSP430FR2153 , MSP430FR2155 , MSP430FR2353 , MSP430FR2355

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
      1.      改訂履歴
  2. 2Device Comparison
    1. 2.1 Related Products
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagrams
    2. 3.2 Pin Attributes
    3. 3.3 Signal Descriptions
    4. 3.4 Pin Multiplexing
    5. 3.5 Buffer Type
    6. 3.6 Connection of Unused Pins
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 4.5  Active Mode Supply Current Per MHz
    6. 4.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 4.7  Low-Power Mode LPM3 and LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 4.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 4.9  Production Distribution of LPM Supply Currents
    10. 4.10 Typical Characteristics - Current Consumption Per Module
    11. 4.11 Thermal Resistance Characteristics
    12. 4.12 Timing and Switching Characteristics
      1. 4.12.1  Power Supply Sequencing
        1. Table 4-1 PMM, SVS and BOR
      2. 4.12.2  Reset Timing
        1. Table 4-2 Wake-up Times From Low-Power Modes and Reset
      3. 4.12.3  Clock Specifications
        1. Table 4-3 XT1 Crystal Oscillator (Low Frequency)
        2. Table 4-4 XT1 Crystal Oscillator (High Frequency)
        3. Table 4-5 DCO FLL, Frequency
        4. Table 4-6 DCO Frequency
        5. Table 4-7 REFO
        6. Table 4-8 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        7. Table 4-9 Module Oscillator (MODOSC)
      4. 4.12.4  Internal Shared Reference
        1. Table 4-10 Internal Shared Reference
      5. 4.12.5  General-Purpose I/Os
        1. Table 4-11 Digital Inputs
        2. Table 4-12 Digital Outputs
      6. 4.12.6  Digital I/O Typical Characteristics
      7. 4.12.7  Timer_B
        1. Table 4-13 Timer_B
      8. 4.12.8  eUSCI
        1. Table 4-14 eUSCI (UART Mode) Clock Frequencies
        2. Table 4-15 eUSCI (UART Mode) Switching Characteristics
        3. Table 4-16 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 4-17 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 4-18 eUSCI (SPI Slave Mode) Switching Characteristics
        6. Table 4-19 eUSCI (I2C Mode) Switching Characteristics
      9. 4.12.9  ADC
        1. Table 4-20 ADC, Power Supply and Input Range Conditions
        2. Table 4-21 ADC, Timing Parameters
        3. Table 4-22 ADC, Linearity Parameters
      10. 4.12.10 Enhanced Comparator (eCOMP)
        1. Table 4-23 eCOMP0
        2. Table 4-24 eCOMP1
      11. 4.12.11 Smart Analog Combo (SAC) (MSP430FR235x Devices Only)
        1. Table 4-25 SAC, OA
        2. Table 4-26 SAC, DAC
      12. 4.12.12 FRAM
        1. Table 4-27 FRAM
      13. 4.12.13 Emulation and Debug
        1. Table 4-28 JTAG, Spy-Bi-Wire Interface
        2. Table 4-29 JTAG, 4-Wire Interface
  5. 5Detailed Description
    1. 5.1  CPU
    2. 5.2  Operating Modes
    3. 5.3  Interrupt Vector Addresses
    4. 5.4  Memory Organization
    5. 5.5  Bootloader (BSL)
    6. 5.6  JTAG Standard Interface
    7. 5.7  Spy-Bi-Wire Interface (SBW)
    8. 5.8  FRAM
    9. 5.9  Memory Protection
    10. 5.10 Peripherals
      1. 5.10.1  Power Management Module (PMM) and On-Chip Reference Voltages
      2. 5.10.2  Clock System (CS) and Clock Distribution
      3. 5.10.3  General-Purpose Input/Output Port (I/O)
      4. 5.10.4  Watchdog Timer (WDT)
      5. 5.10.5  System Module (SYS)
      6. 5.10.6  Cyclic Redundancy Check (CRC)
      7. 5.10.7  Interrupt Compare Controller (ICC)
      8. 5.10.8  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_A1, eUSCI_B0, eUSCI_B1)
      9. 5.10.9  Timers (Timer0_B3, Timer1_B3, Timer2_B3, Timer3_B7)
      10. 5.10.10 Backup Memory (BKMEM)
      11. 5.10.11 Real-Time Clock (RTC) Counter
      12. 5.10.12 12-Bit Analog-to-Digital Converter (ADC)
      13. 5.10.13 Enhanced Comparator
      14. 5.10.14 Manchester Function Module (MFM)
      15. 5.10.15 Smart Analog Combo (SAC) (MSP430FR235x Devices Only)
      16. 5.10.16 eCOMP0, eCOMP1, SAC0, SAC1, SAC2, and SAC3 Interconnection (MSP430FR235x Devices Only)
      17. 5.10.17 Cross-Chip Interconnection (SACx are MSP430FR235x Devices Only)
      18. 5.10.18 Embedded Emulation Module (EEM)
      19. 5.10.19 Peripheral File Map
    11. 5.11 Input/Output Diagrams
      1. 5.11.1 Port P1 Input/Output With Schmitt Trigger
      2. 5.11.2 Port P2 Input/Output With Schmitt Trigger
      3. 5.11.3 Port P3 Input/Output With Schmitt Trigger
      4. 5.11.4 Port P4 Input/Output With Schmitt Trigger
      5. 5.11.5 Port P5 Input/Output With Schmitt Trigger
      6. 5.11.6 Port P6 Input/Output With Schmitt Trigger
    12. 5.12 Device Descriptors (TLV)
    13. 5.13 Identification
      1. 5.13.1 Revision Identification
      2. 5.13.2 Device Identification
      3. 5.13.3 JTAG Identification
  6. 6Applications, Implementation, and Layout
    1. 6.1 Device Connection and Layout Fundamentals
      1. 6.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 6.1.2 External Oscillator
      3. 6.1.3 JTAG
      4. 6.1.4 Reset
      5. 6.1.5 Unused Pins
      6. 6.1.6 General Layout Recommendations
      7. 6.1.7 Do's and Don'ts
    2. 6.2 Peripheral- and Interface-Specific Design Information
      1. 6.2.1 ADC Peripheral
        1. 6.2.1.1 Partial Schematic
        2. 6.2.1.2 Design Requirements
        3. 6.2.1.3 Layout Guidelines
    3. 6.3 ROM Libraries
    4. 6.4 Typical Applications
  7. 7デバイスおよびドキュメントのサポート
    1. 7.1 はじめに
    2. 7.2 デバイスの項目表記
    3. 7.3 ツールとソフトウェア
    4. 7.4 ドキュメントのサポート
    5. 7.5 関連リンク
    6. 7.6 商標
    7. 7.7 静電気放電に関する注意事項
    8. 7.8 Glossary
  8. 8メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

3.2 Pin Attributes

Table 3-1 lists the attributes of all pins.

Table 3-1 Pin Attributes

PIN NUMBER SIGNAL NAME(1)(4) SIGNAL TYPE(2) BUFFER TYPE(3) POWER SOURCE RESET STATE AFTER BOR(5)
PT RHA DBT RSM
1 40 5 32 P1.2 (RD) I/O LVCMOS DVCC OFF
UCB0SIMO I/O LVCMOS DVCC –
UCB0SDA I/O LVCMOS DVCC –
TB0TRG I LVCMOS DVCC –
OA0-(6) I Analog DVCC –
A2 I Analog DVCC –
Veref- I Analog DVCC –
2 1 6 1 P1.1 (RD) I/O LVCMOS DVCC OFF
UCB0CLK I/O LVCMOS DVCC –
ACLK O LVCMOS DVCC –
OA0O(6) O Analog DVCC –
COMP0_1 I Analog DVCC –
A1 I Analog DVCC –
3 2 7 2 P1.0 (RD) I/O LVCMOS DVCC OFF
UCB0STE I/O LVCMOS DVCC –
SMCLK O LVCMOS DVCC –
COMP0_0 I Analog DVCC –
A0 I Analog DVCC –
Veref+ I Analog DVCC –
4 3 8 3 TEST (RD) I LVCMOS DVCC OFF
SBWTCK I LVCMOS DVCC –
5 4 9 4 RST (RD) I/O LVCMOS DVCC OFF
NMI I LVCMOS DVCC –
SBWTDIO I/O LVCMOS DVCC –
6 5 10 5 DVCC P Power DVCC N/A
7 6 11 6 DVSS P Power DVCC N/A
8 7 12 7 P2.7 (RD) I/O LVCMOS DVCC OFF
TB0CLK I LVCMOS DVCC –
XIN I LVCMOS DVCC –
9 8 13 8 P2.6 (RD) I/O LVCMOS DVCC OFF
MCLK O LVCMOS DVCC –
XOUT O LVCMOS DVCC –
10 9 14 9 P2.5 (RD) I/O LVCMOS DVCC OFF
COMP1.0 I Analog DVCC –
11 10 15 10 P2.4 (RD) I/O LVCMOS DVCC OFF
COMP1.1 I Analog DVCC –
12 11 16 11 P4.7 (RD) I/O LVCMOS DVCC OFF
UCB1SOMI(7) I/O LVCMOS DVCC –
UCB1SCL I/O LVCMOS DVCC –
13 12 17 12 P4.6 (RD) I/O LVCMOS DVCC OFF
UCB1SIMO(7) I/O LVCMOS DVCC –
UCB1SDA I/O LVCMOS DVCC –
14 13 18 – P4.5 (RD) I/O LVCMOS DVCC OFF
UCB1CLK I/O LVCMOS DVCC –
15 14 19 – P4.4 (RD) I/O LVCMOS DVCC OFF
UCB1STE I/O LVCMOS DVCC –
16 – – – P6.6 (RD) I/O LVCMOS DVCC OFF
TB3CLK I LVCMOS DVCC –
17 – – – P6.5 (RD) I/O LVCMOS DVCC OFF
TB3.6 I/O LVCMOS DVCC –
18 – – – P6.4 (RD) I/O LVCMOS DVCC OFF
TB3.5 I/O LVCMOS DVCC –
19 – – – P6.3 (RD) I/O LVCMOS DVCC OFF
TB3.4 I/O LVCMOS DVCC –
20 – – – P6.2 (RD) I/O LVCMOS DVCC OFF
TB3.3 I/O LVCMOS DVCC –
21 15 – – P6.1 (RD) I/O LVCMOS DVCC OFF
TB3.2 I/O LVCMOS DVCC –
22 16 – – P6.0 (RD) I/O LVCMOS DVCC OFF
TB3.1 I/O LVCMOS DVCC –
23 17 20 13 P4.3 (RD) I/O LVCMOS DVCC OFF
UCA1TXD O LVCMOS DVCC –
UCA1SIMO I/O LVCMOS DVCC –
UCA1TXD O LVCMOS DVCC –
24 18 21 14 P4.2 (RD) I/O LVCMOS DVCC OFF
UCA1RXD I LVCMOS DVCC –
UCA1SOMI I/O LVCMOS DVCC –
UCA1RXD I LVCMOS DVCC –
25 19 22 15 P4.1 (RD) I/O LVCMOS DVCC OFF
UCA1CLK I/O LVCMOS DVCC –
26 20 23 16 P4.0 (RD) I/O LVCMOS DVCC OFF
UCA1STE I/O LVCMOS DVCC –
ISOTXD O LVCMOS DVCC –
ISORXD I LVCMOS DVCC –
27 21 24 – P2.3 (RD) I/O LVCMOS DVCC OFF
TB1TRG I LVCMOS DVCC –
28 22 25 – P2.2 (RD) I/O LVCMOS DVCC OFF
TB1CLK I LVCMOS DVCC –
29 23 26 17 P2.1(RD) I/O LVCMOS DVCC OFF
TB1.2 I/O LVCMOS DVCC –
COMP1.O O LVCMOS DVCC –
30 24 27 18 P2.0 (RD) I/O LVCMOS DVCC OFF
TB1.1 I/O LVCMOS DVCC –
COMP0.O O LVCMOS DVCC –
31 25 28 19 P1.7 (RD) I/O LVCMOS DVCC OFF
UCA0TXD O LVCMOS DVCC –
UCA0SIMO I/O LVCMOS DVCC –
TB0.2 I/O LVCMOS DVCC –
TDO O LVCMOS DVCC –
OA1+(6) I Analog DVCC –
A7 I Analog DVCC –
VREF+ O Analog DVCC –
32 26 29 20 P1.6 (RD) I/O LVCMOS DVCC OFF
UCA0RXD I LVCMOS DVCC –
UCA0SOMI I/O LVCMOS DVCC –
TB0.1 I/O LVCMOS DVCC –
TDI I LVCMOS DVCC –
TCLK I LVCMOS DVCC –
OA1-(6) I Analog DVCC –
A6 I Analog DVCC –
33 27 30 21 P1.5 (RD) I/O LVCMOS DVCC OFF
UCA0CLK I/O LVCMOS DVCC –
TMS I LVCMOS DVCC –
OA1O(6) O Analog DVCC -
A5 I Analog DVCC –
34 28 31 22 P1.4 (RD) I/O LVCMOS DVCC OFF
UCA0STE I/O LVCMOS DVCC –
TCK I LVCMOS DVCC –
A4 I Analog DVCC –
35 29 32 23 P3.7 (RD) I/O LVCMOS DVCC OFF
OA3+(6) I Analog DVCC –
36 30 33 24 P3.6 (RD) I/O LVCMOS DVCC OFF
OA3-(6) I Analog DVCC –
37 31 34 25 P3.5 (RD) I/O LVCMOS DVCC OFF
OA3O(6) O Analog DVCC –
38 32 35 26 P3.4 (RD) I/O LVCMOS DVCC OFF
SMCLK O LVCMOS DVCC –
39 – – – P5.4 (RD) I/O LVCMOS DVCC OFF
40 – – – P5.3 (RD) I/O LVCMOS DVCC OFF
TB2TRG I LVCMOS DVCC –
A11 I Analog DVCC –
41 – – – P5.2 (RD) I/O LVCMOS DVCC OFF
TB2CLK I LVCMOS DVCC –
A10 I Analog DVCC –
42 33 36 – P5.1 (RD) I/O LVCMOS DVCC OFF
TB2.2 I/O LVCMOS DVCC –
MFM.TX O LVCMOS DVCC –
A9 I Analog DVCC –
43 34 37 – P5.0 (RD) I/O LVCMOS DVCC OFF
TB2.1 I/O LVCMOS DVCC –
MFM.RX I LVCMOS DVCC –
A8 I Analog DVCC –
44 35 38 27 P3.3 (RD) I/O LVCMOS DVCC OFF
OA2+(6) I Analog DVCC –
45 36 1 28 P3.2 (RD) I/O LVCMOS DVCC OFF
OA2-(6) I Analog DVCC –
46 37 2 29 P3.1 (RD) I/O LVCMOS DVCC OFF
OA2O(6) O Analog DVCC –
47 38 3 30 P3.0 (RD) I/O LVCMOS DVCC OFF
MCLK O LVCMOS DVCC –
48 39 4 31 P1.3 (RD) I/O LVCMOS DVCC OFF
UCB0SOMI I/O LVCMOS DVCC –
UCB0SCL I/O LVCMOS DVCC –
OA0+(6) I Analog DVCC –
A3 I Analog DVCC –
(1) Signals names with (RD) denote the reset default pin name.
(2) Signal types: I = input, O = output, I/O = input or output
(3) Buffer types: LVCMOS, analog, or power
(4) To determine the pin mux encodings for each pin, see Section 5.11.
(5) Reset states:
OFF = High-impedance input with pullup or pulldown disabled (if available)
N/A = Not applicable
(6) MSP430FR235x devices only
(7) Not applicable in RSM package.