JAJSD97 データシート

JAJSD97 April 2017 MSP430FR5989-EP

PRODUCTION DATA.

パッケージ・オプション

4 Specifications

4.1 Absolute Maximum Ratings⁽¹⁾

over operating junction temperature range (unless otherwise noted)

	MIN	MAX	UNIT
Voltage applied at DVCC and AVCC pins to V_SS	–0.3	4.1	V
Voltage difference between DVCC and AVCC pins⁽²⁾		±0.3	V
Voltage applied to any pin⁽³⁾	–0.3	V_CC + 0.3 V (4.1 max)	V
Diode current at any device pin		±2	mA
Storage temperature, T_stg⁽⁴⁾	–55	125	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Voltage differences between DVCC and AVCC exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM.

(3) All voltage values are with respect to V_SS, unless otherwise noted.

(4) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

4.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±1000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±250	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V may actually have higher performance.

4.3 Recommended Operating Conditions

Typical data are based on V_CC = 3 V, T_J = 25°C unless otherwise noted.

			MIN	NOM	MAX	UNIT
V_CC	Supply voltage range applied at all DVCC, AVCC, and ESIDVCC pins⁽¹⁾ ⁽²⁾ ⁽³⁾		1.8⁽⁶⁾		3.6	V
V_SS	Supply voltage applied at all DVSS, AVSS, and ESIDVSS pins			0		V
T_J	Operating junction temperature		–55		95	°C
C_DVCC	Capacitor value at DVCC and ESIDVCC⁽⁴⁾		1_–20%			µF
f_SYSTEM	Processor frequency (maximum MCLK frequency)⁽⁵⁾	No FRAM wait states (NWAITSx = 0)	0		8⁽⁸⁾	MHz
f_SYSTEM	Processor frequency (maximum MCLK frequency)⁽⁵⁾	With FRAM wait states (NWAITSx = 1)⁽⁷⁾	0		16⁽⁹⁾	MHz
f_ACLK	Maximum ACLK frequency				50	kHz
f_SMCLK	Maximum SMCLK frequency				16⁽⁹⁾	MHz

(1) TI recommends powering the DVCC, AVCC, and ESIDVCC pins from the same source. At a minimum, during power up, power down, and device operation, the voltage difference between DVCC, AVCC, and ESIDVCC must not exceed the limits specified in Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM.

(2) See Table 4-1 for additional important information.

(3) Modules may have a different supply voltage range specification. See the specification of each module in this data sheet.

(4) Connect a low-ESR capacitor with at least the value specified and a maximum tolerance of 20% as close as possible to the DVCC and ESIDVCC pins.

(5) Modules may have a different maximum input clock specification. See the specification of each module in this data sheet.

(6) The minimum supply voltage is defined by the supervisor SVS levels. See Table 4-2 for the exact values.

(7) Wait states only occur on actual FRAM accesses; that is, on FRAM cache misses. RAM and peripheral accesses are always executed without wait states.

(8) DCO settings and HF crystals with a typical value less than or equal to the specified MAX value are permitted.

(9) DCO settings and HF crystals with a typical value less than or equal to the specified MAX value are permitted. If a clock sources with a larger typical value is used, the clock must be divided in the clock system.

4.4 Active Mode Supply Current Into V_CC Excluding External Current

over recommended operating junction temperature (unless otherwise noted)⁽¹⁾ ⁽²⁾

PARAMETER	EXECUTION MEMORY	V_CC	FREQUENCY (f_MCLK = f_SMCLK)										UNIT
			1 MHz 0 WAIT STATES (NWAITSx = 0)		4 MHz 0 WAIT STATES (NWAITSx = 0)		8 MHz 0 WAIT STATES (NWAITSx = 0)		12 MHz 1 WAIT STATE (NWAITSx = 1)		16 MHz 1 WAIT STATE (NWAITSx = 1)
			TYP	MAX	TYP	MAX	TYP	MAX	TYP	MAX	TYP	MAX
I_{AM, FRAM_UNI} (Unified memory)⁽³⁾	FRAM	3.0 V	210		640		1220		1475		1845		µA
I_{AM, FRAM}(0%)⁽⁴⁾ ⁽⁵⁾	FRAM 0% cache hit ratio	3.0 V	375		1290		2525		2100		2675		µA
I_{AM, FRAM}(50%)⁽⁴⁾ ⁽⁵⁾	FRAM 50% cache hit ratio	3.0 V	240		745		1440		1575		1990		µA
I_{AM, FRAM}(66%)⁽⁴⁾ ⁽⁵⁾	FRAM 66% cache hit ratio	3.0 V	200		560		1070		1300		1620		µA
I_{AM, FRAM}(75%)⁽⁴⁾ ⁽⁵⁾	FRAM 75% cache hit ratio	3.0 V	170	255	480		890	1085	1155	1310	1420	1620	µA
I_{AM, FRAM}(100%⁽⁴⁾ ⁽⁵⁾	FRAM 100% cache hit ratio	3.0 V	110		235		420		640		730		µA
I_{AM, RAM} ⁽⁶⁾ ⁽⁵⁾	RAM	3.0 V	130		320		585		890		1070		µA
I_{AM, RAM only} ⁽⁷⁾ ⁽⁵⁾	RAM	3.0 V	100	180	290		555		860		1040	1300	µA

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) Characterized with program executing typical data processing.
f_ACLK = 32768 Hz, f_MCLK = f_SMCLK = f_DCO at specified frequency, except for 12 MHz. For 12 MHz, f_DCO = 24 MHz and f_MCLK = f_SMCLK = f_DCO / 2.
At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency (f_MCLK,eff) decreases. The effective MCLK frequency also depends on the cache hit ratio. SMCLK is not affected by the number of wait states or the cache hit ratio.
The following equation can be used to compute f_MCLK,eff:
f_MCLK,eff = f_MCLK / [wait states × (1 – cache hit ratio) + 1]
For example, with 1 wait state and 75% cache hit ratio f_MCKL,eff = f_MCLK / [1 × (1 – 0.75) + 1] = f_MCLK / 1.25.

(3) Represents typical program execution. Program and data reside entirely in FRAM. All execution is from FRAM.

(4) Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit ratio represents number cache accesses divided by the total number of FRAM accesses. For example, a 75% ratio implies three of every four accesses is from cache, and the remaining are FRAM accesses.

(5) See Figure 4-1 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best linear fit using the typical data shown in Section 4.4.

(6) Program and data reside entirely in RAM. All execution is from RAM.

(7) Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.

4.5 Typical Characteristics, Active Mode Supply Currents

I(AM, cache hit ratio): Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit ratio represents number cache accesses divided by the total number of FRAM accesses. For example, a 75% ratio implies three of every four accesses is from cache, and the remaining are FRAM accesses.

I(AM, RAMonly): Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.

Figure 4-1 Typical Active Mode Supply Currents, No Wait States

4.6 Low-Power Mode (LPM0, LPM1) Supply Currents Into V_CC Excluding External Current

over recommended operating junction temperature (unless otherwise noted)⁽¹⁾ ⁽²⁾

PARAMETER	V_CC	FREQUENCY (f_SMCLK)										UNIT
		1 MHz		4 MHz		8 MHz		12 MHz		16 MHz
		TYP	MAX	TYP	MAX	TYP	MAX	TYP	MAX	TYP	MAX
I_LPM0	2.2 V	75		105		165		250		230		µA
I_LPM0	3.0 V	85	120	115		175		260		240	275	µA
I_LPM1	2.2 V	40		65		130		215		195		µA
I_LPM1	3.0 V	40	65	65		130		215		195	220	µA

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) Current for watchdog timer clocked by SMCLK included.
f_ACLK = 32768 Hz, f_MCLK = 0 MHz, f_SMCLK = f_DCO at specified frequency, except for 12 MHz: here f_DCO = 24 MHz and f_SMCLK = f_DCO / 2.

4.7 Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into V_CC) Excluding External Current

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted) ⁽¹⁾

PARAMETER		V_CC	TEMPERATURE (T_J)								UNIT
			–55°C		25°C		60°C		95°C
			TYP	MAX	TYP	MAX	TYP	MAX	TYP	MAX
I_LPM2,XT12	Low-power mode 2, 12-pF crystal⁽¹⁾ ⁽³⁾ ⁽⁴⁾	2.2 V	0.6		1.2		3.1		8.8		μA
I_LPM2,XT12	Low-power mode 2, 12-pF crystal⁽¹⁾ ⁽³⁾ ⁽⁴⁾	3.0 V	0.6		1.2	2.2	3.1		8.8	20.8	μA
I_LPM2,XT3.7	Low-power mode 2, 3.7-pF crystal⁽¹⁾ ⁽²⁾ ⁽⁴⁾	2.2 V	0.5		1.1		3.0		8.7		μA
I_LPM2,XT3.7	Low-power mode 2, 3.7-pF crystal⁽¹⁾ ⁽²⁾ ⁽⁴⁾	3.0 V	0.5		1.1		3.0		8.7		μA
I_LPM2,VLO	Low-power mode 2, VLO, includes SVS⁽⁵⁾	2.2 V	0.3		0.9		2.8		8.5		μA
I_LPM2,VLO	Low-power mode 2, VLO, includes SVS⁽⁵⁾	3.0 V	0.3		0.9	2.0	2.8		8.5	20.5	μA
I_LPM3,XT12	Low-power mode 3, 12-pF crystal, excludes SVS⁽¹⁾ ⁽³⁾ ⁽⁶⁾	2.2 V	0.5		0.7		1.2		2.5		μA
I_LPM3,XT12	Low-power mode 3, 12-pF crystal, excludes SVS⁽¹⁾ ⁽³⁾ ⁽⁶⁾	3.0 V	0.5		0.7	1.0	1.2		2.5	6.4	μA
I_LPM3,XT3.7	Low-power mode 3, 3.7-pF crystal, excludes SVS⁽¹⁾ ⁽²⁾ ⁽⁷⁾ (also see Figure 4-2)	2.2 V	0.4		0.6		1.1		2.4		μA
I_LPM3,XT3.7		3.0 V	0.4		0.6		1.1		2.4		μA
I_LPM3,VLO	Low-power mode 3, VLO, excludes SVS ⁽⁸⁾	2.2 V	0.3		0.4		0.9		2.2		μA
I_LPM3,VLO	Low-power mode 3, VLO, excludes SVS ⁽⁸⁾	3.0 V	0.3		0.4	0.8	0.9		2.2	6.1	μA
I_{LPM3,VLO, RAMoff}	Low-power mode 3, VLO, excludes SVS, RAM powered-down completely⁽⁹⁾	2.2 V	0.3		0.4		0.8		2.1		μA
I_{LPM3,VLO, RAMoff}		3.0 V	0.3		0.4	0.7	0.8		2.1	5.2	μA
I_LPM4,SVS	Low-power mode 4, includes SVS⁽¹⁰⁾	2.2 V	0.4		0.5		0.9		2.3		μA
I_LPM4,SVS	Low-power mode 4, includes SVS⁽¹⁰⁾	3.0 V	0.4		0.5	0.8	0.9		2.3	6.2	μA
I_LPM4	Low-power mode 4, excludes SVS⁽¹¹⁾	2.2 V	0.2		0.3		0.7		2.0		μA
I_LPM4	Low-power mode 4, excludes SVS⁽¹¹⁾	3.0 V	0.2		0.3	0.6	0.7		2.0	6.0	μA
I_LPM4,RAMoff	Low-power mode 4, excludes SVS, RAM powered-down completely⁽¹²⁾	2.2 V	0.2		0.3		0.7		1.9		μA
I_LPM4,RAMoff		3.0 V	0.2		0.3	0.6	0.7		1.9	5.1	μA
I_IDLE,GroupA	Additional idle current if one or more modules from Group A (see Table 5-3) are activated in LPM3 or LPM4	3.0V			0.02				1.18	2.6	μA
I_IDLE,GroupB	Additional idle current if one or more modules from Group B (see Table 5-3) are activated in LPM3 or LPM4	3.0V			0.02				1.15	2.6	μA
I_IDLE,GroupC	Additional idle current if one or more modules from Group C (see Table 5-3) are activated in LPM3 or LPM4	3.0V			0.02				1.5	2.8	μA
I_IDLE,GroupD	Additional idle current if one or more modules from Group D (see Table 5-3) are activated in LPM3 or LPM4	3.0V			0.015				1.4	2.4	μA

(1) Not applicable for devices with HF crystal oscillator only.

(2) Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are chosen to closely match the required 3.7-pF load.

(3) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF load.

(4) Low-power mode 2, crystal oscillator test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),
f_XT1 = 32768 Hz, f_ACLK = f_XT1, f_MCLK = f_SMCLK = 0 MHz

(5) Low-power mode 2, VLO test conditions:
Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). Current for brownout and SVS included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),
f_XT1 = 0 Hz, f_ACLK = f_VLO, f_MCLK = f_SMCLK = 0 MHz

(6) Low-power mode 3, 12-pF crystal excluding SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
f_XT1 = 32768 Hz, f_ACLK = f_XT1, f_MCLK = f_SMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional idle current. See the idle currents specified for the respective peripheral groups.

(7) Low-power mode 3, 3.7-pF crystal excluding SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
f_XT1 = 32768 Hz, f_ACLK = f_XT1, f_MCLK = f_SMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional idle current. See the idle currents specified for the respective peripheral groups.

(8) Low-power mode 3, VLO excluding SVS test conditions:
Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
f_XT1 = 0 Hz, f_ACLK = f_VLO, f_MCLK = f_SMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional idle current. See the idle currents specified for the respective peripheral groups.

(9) Low-power mode 3, VLO excluding SVS test conditions:
Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). RAM disabled (RCCTL0 = 5A55h). Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
f_XT1 = 0 Hz, f_ACLK = f_VLO, f_MCLK = f_SMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional idle current. See the idle currents specified for the respective peripheral groups.

(10) Low-power mode 4 including SVS test conditions:
Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
f_XT1 = 0 Hz, f_ACLK = 0 Hz, f_MCLK = f_SMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional idle current. See the idle currents specified for the respective peripheral groups.

(11) Low-power mode 4 excluding SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
f_XT1 = 0 Hz, f_ACLK = 0 Hz, f_MCLK = f_SMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional idle current. See the idle currents specified for the respective peripheral groups.

(12) Low-power mode 4 excluding SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). RAM disabled (RCCTL0 = 5A55h).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
f_XT1 = 0 Hz, f_ACLK = 0 Hz, f_MCLK = f_SMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional idle current. See the idle currents specified for the respective peripheral groups.

4.8 Low-Power Mode With LCD Supply Currents (Into V_CC) Excluding External Current

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER		V_CC	TEMPERATURE (T_J)								UNIT
			–55°C		25°C		60°C		95°C
			TYP	MAX	TYP	MAX	TYP	MAX	TYP	MAX
I_LPM3,XT12 LCD, ext. bias	Low-power mode 3 (LPM3) current,12-pF crystal, LCD 4-mux mode, external biasing, excludes SVS⁽¹⁾ ⁽²⁾	3.0 V	0.7		0.9		1.5		3.1		µA
I_LPM3,XT12 LCD, int. bias	Low-power mode 3 (LPM3) current, 12-pF crystal, LCD 4-mux mode, internal biasing, charge pump disabled, excludes SVS⁽¹⁾ ⁽³⁾	3.0 V	2.0		2.2	2.9	2.8		4.4	9.3	µA
I_LPM3,XT12 LCD,CP	Low-power mode 3 (LPM3) current,12-pF crystal, LCD 4-mux mode, internal biasing, charge pump enabled, 1/3 bias, excludes SVS⁽¹⁾ ⁽⁴⁾	2.2 V	5.0		5.2		5.8		7.4		µA
I_LPM3,XT12 LCD,CP		3.0 V	4.5		4.7		5.3		6.9		µA

(1) Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
f_XT1 = 32768 Hz, f_ACLK = f_XT1, f_MCLK = f_SMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional idle current - idle current of Group containing LCD module already included. See the idle currents specified for the respective peripheral groups.

(2) LCDMx = 11 (4-mux mode), LCDREXT = 1, LCDEXTBIAS = 1 (external biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (f_LCD = 32768 Hz / 32 / 4 = 256 Hz)
Current through external resistors not included (voltage levels are supplied by test equipment).
Even segments S0, S2, ... = 0, odd segments S1, S3, ... = 1. No LCD panel load.

(3) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (f_LCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2, ...=0, odd segments S1, S3, ... = 1. No LCD panel load.

(4) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump enabled), VLCDx = 1000 (V_LCD= 3 V typical), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (f_LCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2, ...=0, odd segments S1, S3, ... = 1. No LCD panel load. C_LCDCAP = 10 µF

4.9 Low-Power Mode LPMx.5 Supply Currents (Into V_CC) Excluding External Current

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)⁽¹⁾

PARAMETER		V_CC	–55°C		25°C		60°C		95°C		UNIT
PARAMETER		V_CC	TYP	MAX	TYP	MAX	TYP	MAX	TYP	MAX	UNIT
I_LPM3.5,XT12	Low-power mode 3.5, 12-pF crystal including SVS⁽¹⁾ ⁽³⁾ ⁽⁴⁾	2.2 V	0.4		0.45		0.55		0.75		μA
I_LPM3.5,XT12	Low-power mode 3.5, 12-pF crystal including SVS⁽¹⁾ ⁽³⁾ ⁽⁴⁾	3.0 V	0.4		0.45	0.7	0.55		0.75	1.6	μA
I_LPM3.5,XT3.7	Low-power mode 3.5, 3.7-pF crystal excluding SVS⁽¹⁾ ⁽²⁾ ⁽⁵⁾	2.2 V	0.3		0.35		0.4		0.65		μA
I_LPM3.5,XT3.7	Low-power mode 3.5, 3.7-pF crystal excluding SVS⁽¹⁾ ⁽²⁾ ⁽⁵⁾	3.0 V	0.3		0.35		0.4		0.65		μA
I_LPM4.5,SVS	Low-power mode 4.5, including SVS⁽⁶⁾	2.2 V	0.2		0.2		0.25		0.35		μA
I_LPM4.5,SVS	Low-power mode 4.5, including SVS⁽⁶⁾	3.0 V	0.2		0.2	0.4	0.25		0.35	0.7	μA
I_LPM4.5	Low-power mode 4.5, excluding SVS⁽⁷⁾	2.2 V	0.02		0.02		0.03		0.14		μA
I_LPM4.5	Low-power mode 4.5, excluding SVS⁽⁷⁾	3.0 V	0.02		0.02		0.03		0.13	0.5	μA

(1) Not applicable for devices with HF crystal oscillator only.

(2) Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are chosen to closely match the required 3.7-pF load.

(3) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF load.

(4) Low-power mode 3.5, 1-pF crystal including SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
f_XT1 = 32768 Hz, f_ACLK = f_XT1, f_MCLK = f_SMCLK = 0 MHz

(5) Low-power mode 3.5, 3.7-pF crystal excluding SVS test conditions:
Current for RTC clocked by XT1 included.Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
f_XT1 = 32768 Hz, f_ACLK = f_XT1, f_MCLK = f_SMCLK = 0 MHz

(6) Low-power mode 4.5 including SVS test conditions:
Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
f_XT1 = 0 Hz, f_ACLK = 0 Hz, f_MCLK = f_SMCLK = 0 MHz

(7) Low-power mode 4.5 excluding SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
f_XT1 = 0 Hz, f_ACLK = 0 Hz, f_MCLK = f_SMCLK = 0 MHz

4.10 Typical Characteristics, Low-Power Mode Supply Currents

Figure 4-2 LPM3 Supply Current vs Temperature (LPM3, XT3.7)

Figure 4-4 LPM3.5 Supply Current vs Temperature (LPM3.5, XT3.7)

Figure 4-3 LPM4 Supply Current vs Temperature (LPM4, SVS)

Figure 4-5 LPM4.5 Supply Current vs Temperature (LPM4.5)

4.11 Typical Characteristics, Current Consumption per Module⁽¹⁾

MODULE	TEST CONDITIONS	REFERENCE CLOCK	TYP	UNIT
Timer_A		Module input clock	3	μA/MHz
Timer_B		Module input clock	5	μA/MHz
eUSCI_A	UART mode	Module input clock	5.5	μA/MHz
eUSCI_A	SPI mode	Module input clock	3.5	μA/MHz
eUSCI_B	SPI mode	Module input clock	3.5	μA/MHz
eUSCI_B	I²C mode, 100 kbaud	Module input clock	3.5	μA/MHz
RTC_C		32 kHz	100	nA
MPY	Only from start to end of operation	MCLK	25	μA/MHz
AES	Only from start to end of operation	MCLK	21	μA/MHz
CRC16	Only from start to end of operation	MCLK	2.5	μA/MHz
CRC32	Only from start to end of operation	MCLK	2.5	μA/MHz

(1) LCD_C: See Section 4.8. For other module currents not listed here, see the module-specific parameter sections.

4.12 Thermal Resistance Characteristics

THERMAL METRIC⁽¹⁾		MSP430FR5989-EP	UNIT
		RGC (VQFN)
		64 Pins
R_θJA	Junction-to-ambient thermal resistance, still air⁽²⁾	29.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance⁽³⁾	13.9	°C/W
R_θJB	Junction-to-board thermal resistance⁽⁵⁾	8.1	°C/W
Ψ_JT	Junction-to-top thermal characterization parameter	8.0	°C/W
Ψ_JB	Junction-to-board thermal characterization parameter	0.2	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance⁽⁴⁾	1.0	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(5) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.

4.13 Timing and Switching Characteristics

4.13.1 Power Supply Sequencing

TI recommends powering the AVCC, DVCC, and ESIDVCC pins from the same source. At a minimum, during power up, power down, and device operation, the voltage difference between AVCC, DVCC, and ESIDVCC must not exceed the limits specified in Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM.

At power up, the device does not start executing code before the supply voltage reached V_SVSH+ if the supply rises monotonically to this level.

Table 4-1 lists the power ramp requirements.

Table 4-1 Brownout and Device Reset Power Ramp Requirements

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
V_{VCC_BOR–}	Brownout power-down level⁽¹⁾⁽²⁾	\| dDV_CC/d_t \| < 3 V/s⁽³⁾	0.7	1.66	V
V_{VCC_BOR–}	Brownout power-down level⁽¹⁾⁽²⁾	\| dDV_CC/d_t \| > 300 V/s⁽³⁾	0		V
V_{VCC_BOR+}	Brownout power-up level⁽²⁾	\| dDV_CC/d_t \| < 3 V/s⁽⁴⁾	0.79	1.68	V

(1) In case of a supply voltage brownout, the device supply voltages must ramp down to the specified brownout power-down level (V_{VCC_BOR-}) before the voltage is ramped up again to ensure a reliable device start-up and performance according to the data sheet including the correct operation of the on-chip SVS module.

(2) Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the data sheet recommendation for capacitor C_DVCC should limit the slopes accordingly.

(3) The brownout levels are measured with a slowly changing supply. With faster slopes, the MIN level required to reset the device properly can decrease to 0 V. Use the graph in Figure 4-6 to estimate the V_{VCC_BOR-} level based on the down slope of the supply voltage. After removing V_CC, the down slope can be estimated based on the current consumption and the capacitance on DVCC: dV/dt = I/C where dV/dt = slope, I = current, C = capacitance.

(4) The brownout levels are measured with a slowly changing supply.

Figure 4-6 Brownout Power-Down Level vs Supply Voltage Down Slope

Table 4-2 lists the characteristics of the SVS.

Table 4-2 SVS

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
I_SVSH,LPM	SVS_H current consumption, low-power modes			170	300	nA
V_SVSH-	SVS_H power-down level		1.74	1.81	1.86	V
V_SVSH+	SVS_H power-up level		1.76	1.88	1.99	V
V_{SVSH_hys}	SVS_H hysteresis		40		120	mV
t_{PD,SVSH, AM}	SVS_H propagation delay, active mode	dV_Vcc/dt = –10 mV/µs		10		µs

4.13.2 Reset Timing

Table 4-3 lists the input requirements for the RST signal.

Table 4-3 Reset Input

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER		V_CC	MIN	MAX	UNIT
t_(RST)	External reset pulse duration on RST⁽¹⁾	2.2 V, 3.0 V	2		µs

(1) Not applicable if the RST/NMI pin is configured as NMI.

4.13.3 Clock Specifications

Table 4-4 lists the characteristics of the LFXT.

Table 4-4 Low-Frequency Crystal Oscillator, LFXT⁽⁴⁾

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
I_VCC.LFXT	Current consumption	f_OSC = 32768 Hz, LFXTBYPASS = 0, LFXTDRIVE = {0}, T_J = 25°C, C_L,eff = 3.7 pF, ESR ≈ 44 kΩ	3.0 V		180		nA
		f_OSC = 32768 Hz, LFXTBYPASS = 0, LFXTDRIVE = {1}, T_J = 25°C, C_L,eff = 6 pF, ESR ≈ 40 kΩ	3.0 V		185
		f_OSC = 32768 Hz, LFXTBYPASS = 0, LFXTDRIVE = {2}, T_J = 25°C, C_L,eff = 9 pF, ESR ≈ 40 kΩ	3.0 V		225
		f_OSC = 32768 Hz, LFXTBYPASS = 0, LFXTDRIVE = {3}, T_J = 25°C, C_L,eff = 12.5 pF, ESR ≈ 40 kΩ	3.0 V		330
f_LFXT	LFXT oscillator crystal frequency	LFXTBYPASS = 0			32768		Hz
DC_LFXT	LFXT oscillator duty cycle	Measured at ACLK, f_LFXT = 32768 Hz		30%		70%
f_LFXT,SW	LFXT oscillator logic-level square-wave input frequency	LFXTBYPASS = 1⁽⁵⁾ ⁽⁸⁾		10.5	32.768	50	kHz
DC_{LFXT, SW}	LFXT oscillator logic-level square-wave input duty cycle	LFXTBYPASS = 1		30%		70%
OA_LFXT	Oscillation allowance for LF crystals⁽⁹⁾	LFXTBYPASS = 0, LFXTDRIVE = {1}, f_LFXT = 32768 Hz, C_L,eff = 6 pF			210		kΩ
OA_LFXT	Oscillation allowance for LF crystals⁽⁹⁾	LFXTBYPASS = 0, LFXTDRIVE = {3}, f_LFXT = 32768 Hz, C_L,eff = 12.5 pF			300		kΩ
C_LFXIN	Integrated load capacitance at LFXIN terminal⁽⁶⁾ ⁽⁷⁾				2		pF
C_LFXOUT	Integrated load capacitance at LFXOUT terminal⁽⁶⁾ ⁽⁷⁾				2		pF
t_START,LFXT	Start-up time⁽²⁾	f_OSC = 32768 Hz, LFXTBYPASS = 0, LFXTDRIVE = {0}, T_J = 25°C, C_L,eff = 3.7 pF	3.0 V		800		ms
t_START,LFXT	Start-up time⁽²⁾	f_OSC = 32768 Hz, LFXTBYPASS = 0, LFXTDRIVE = {3}, T_J = 25°C, C_L,eff = 12.5 pF	3.0 V		1000		ms
f_Fault,LFXT	Oscillator fault frequency⁽³⁾ ⁽¹⁾			0		3500	Hz

(1) Measured with logic-level input frequency but also applies to operation with crystals.

(2) Includes start-up counter of 1024 clock cycles.

(3) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specification may set the flag. A static condition or stuck at fault condition sets the flag.

(4) To improve EMI on the LFXT oscillator, observe the following guidelines.

Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins LFXIN and LFXOUT.
Avoid running PCB traces underneath or adjacent to the LFXIN and LFXOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator LFXIN and LFXOUT pins.
If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.

(5) When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DC_{LFXT, SW}.

(6) This represents all the parasitic capacitance present at the LFXIN and LFXOUT terminals, respectively, including parasitic bond and package capacitance. The effective load capacitance, C_L,eff can be computed as C_IN x C_OUT / (C_IN + C_OUT), where C_IN and C_OUT are the total capacitance at the LFXIN and LFXOUT terminals, respectively.

(7) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF. The PCB adds additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance of the selected crystal is met.

(8) Maximum frequency of operation of the entire device cannot be exceeded.

(9) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following guidelines, but should be evaluated based on the actual crystal selected for the application:

For LFXTDRIVE = {0}, C_L,eff = 3.7 pF.
For LFXTDRIVE = {1}, C_L,eff = 6 pF
For LFXTDRIVE = {2}, 6 pF ≤ C_L,eff ≤ 9 pF
For LFXTDRIVE = {3}, 9 pF ≤ C_L,eff ≤ 12.5 pF

Table 4-5 lists the characteristics of the HFXT.

Table 4-5 High-Frequency Crystal Oscillator, HFXT⁽⁵⁾

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
I_DVCC.HFXT	HFXT oscillator crystal current HF mode at typical ESR	f_OSC = 4 MHz, HFXTBYPASS = 0, HFXTDRIVE = 0, HFFREQ = 1⁽⁸⁾ T_J = 25°C, C_L,eff = 18 pF, Typical ESR, C_shunt	3.0 V		75		μA
		f_OSC = 8 MHz, HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 1, T_J = 25°C, C_L,eff = 18 pF, Typical ESR, C_shunt			120
		f_OSC = 16 MHz, HFXTBYPASS = 0, HFXTDRIVE = 2, HFFREQ = 2, T_J = 25°C, C_L,eff = 18 pF, Typical ESR, C_shunt			190
		f_OSC = 24 MHz, HFXTBYPASS = 0, HFXTDRIVE = 3, HFFREQ = 3, T_J = 25°C, C_L,eff = 18 pF, Typical ESR, C_shunt			250
f_HFXT	HFXT oscillator crystal frequency, crystal mode	HFXTBYPASS = 0, HFFREQ = 1⁽⁸⁾⁽⁷⁾		4		8	MHz
		HFXTBYPASS = 0, HFFREQ = 2⁽⁷⁾		8.01		16
		HFXTBYPASS = 0, HFFREQ = 3⁽⁷⁾		16.01		24
DC_HFXT	HFXT oscillator duty cycle	Measured at SMCLK, f_HFXT = 16 MHz		40%	50%	60%
f_HFXT,SW	HFXT oscillator logic-level square-wave input frequency, bypass mode	HFXTBYPASS = 1, HFFREQ = 0⁽⁶⁾⁽⁷⁾		0.9		4	MHz
		HFXTBYPASS = 1, HFFREQ = 1⁽⁶⁾⁽⁷⁾		4.01		8
		HFXTBYPASS = 1, HFFREQ = 2⁽⁶⁾⁽⁷⁾		8.01		16
		HFXTBYPASS = 1, HFFREQ = 3⁽⁶⁾⁽⁷⁾		16.01		24
DC_{HFXT, SW}	HFXT oscillator logic-level square-wave input duty cycle	HFXTBYPASS = 1		40%		60%
t_START,HFXT	Start-up time⁽⁹⁾	f_OSC = 4 MHz, HFXTBYPASS = 0, HFXTDRIVE = 0, HFFREQ = 1, T_J = 25°C, C_L,eff = 16 pF	3.0 V		1.6		ms
t_START,HFXT	Start-up time⁽⁹⁾	f_OSC = 24 MHz , HFXTBYPASS = 0, HFXTDRIVE = 3, HFFREQ = 3, T_J = 25°C, C_L,eff = 16 pF	3.0 V		0.6		ms
C_HFXIN	Integrated load capacitance at HFXIN terminaI⁽¹⁾ ⁽²⁾				2		pF
C_HFXOUT	Integrated load capacitance at HFXOUT terminaI⁽¹⁾ ⁽²⁾				2		pF
f_Fault,HFXT	Oscillator fault frequency⁽⁴⁾ ⁽³⁾			0		800	kHz

(1) This represents all the parasitic capacitance present at the HFXIN and HFXOUT terminals, respectively, including parasitic bond and package capacitance. The effective load capacitance, C_L,eff can be computed as C_IN x C_OUT / (C_IN + C_OUT), where C_IN and C_OUT is the total capacitance at the HFXIN and HFXOUT terminals, respectively.

(2) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended effective load capacitance values supported are 14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF. The PCB adds additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance of the selected crystal is met.

(3) Measured with logic-level input frequency but also applies to operation with crystals.

(4) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX might set the flag. A static condition or stuck at fault condition set the flag.

(5) To improve EMI on the HFXT oscillator, observe the following guidelines.

Keep the traces between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins HFXIN and HFXOUT.
Avoid running PCB traces underneath or adjacent to the HFXIN and HFXOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator HFXIN and HFXOUT pins.
If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.

(6) When HFXTBYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DC_{HFXT, SW}.

(7) Maximum frequency of operation of the entire device cannot be exceeded.

(8) HFFREQ = {0} is not supported for HFXT crystal mode of operation.

(9) Includes start-up counter of 1024 clock cycles.

Table 4-6 lists the characteristics of the DCO.

Table 4-6 DCO

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
f_DCO1	DCO frequency range 1 MHz, trimmed	Measured at SMCLK, divide by 1, DCORSEL = 0, DCOFSEL = 0, DCORSEL = 1, DCOFSEL = 0			1	±3.5%	MHz
f_DCO2.7	DCO frequency range 2.7 MHz, trimmed	Measured at SMCLK, divide by 1, DCORSEL = 0, DCOFSEL = 1			2.667	±3.5%	MHz
f_DCO3.5	DCO frequency range 3.5 MHz, trimmed	Measured at SMCLK, divide by 1, DCORSEL = 0, DCOFSEL = 2			3.5	±3.5%	MHz
f_DCO4	DCO frequency range 4 MHz, trimmed	Measured at SMCLK, divide by 1, DCORSEL = 0, DCOFSEL = 3			4	±3.5%	MHz
f_DCO5.3	DCO frequency range 5.3 MHz, trimmed	Measured at SMCLK, divide by 1, DCORSEL = 0, DCOFSEL = 4, DCORSEL = 1, DCOFSEL = 1			5.333	±3.5%	MHz
f_DCO7	DCO frequency range 7 MHz, trimmed	Measured at SMCLK, divide by 1, DCORSEL = 0, DCOFSEL = 5, DCORSEL = 1, DCOFSEL = 2			7	±3.5%	MHz
f_DCO8	DCO frequency range 8 MHz, trimmed	Measured at SMCLK, divide by 1, DCORSEL = 0, DCOFSEL = 6, DCORSEL = 1, DCOFSEL = 3			8	±3.5%	MHz
f_DCO16	DCO frequency range 16 MHz, trimmed	Measured at SMCLK, divide by 1, DCORSEL = 1, DCOFSEL = 4			16	±3.5%⁽²⁾	MHz
f_DCO21	DCO frequency range 21 MHz, trimmed	Measured at SMCLK, divide by 2, DCORSEL = 1, DCOFSEL = 5			21	±3.5%⁽²⁾	MHz
f_DCO24	DCO frequency range 24 MHz, trimmed	Measured at SMCLK, divide by 2, DCORSEL = 1, DCOFSEL = 6			24	±3.5%⁽²⁾	MHz
f_DCO,DC	Duty cycle	Measured at SMCLK, divide by 1, no external divide, all DCORSEL/DCOFSEL settings except DCORSEL = 1, DCOFSEL = 5 and DCORSEL = 1, DCOFSEL = 6		48%	50%	52%
t_{DCO, JITTER}	DCO jitter	Based on f_signal = 10 kHz and DCO used for 12-bit SAR ADC sampling source. This achieves >74 dB SNR due to jitter (that is, it is limited by ADC performance).			2	3	ns
df_DCO/dT	DCO temperature drift⁽¹⁾		3.0 V		0.01		%/°C

(1) Calculated using the box method: (MAX(–55°C to 95°C) – MIN(–55°C to 95°C)) / MIN(–55°C to 95°C) / (95°C – (–55°C))

(2) After a wakeup from LPM1, LPM2, LPM3, or LPM4, the DCO frequency f_DCO might exceed the specified frequency range for a few clock cycles by up to 5% before settling into the specified steady-state frequency range.

Table 4-7 lists the characteristics of the VLO.

Table 4-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
I_VLO	Current consumption			100		nA
f_VLO	VLO frequency	Measured at ACLK	5	9.9	15	kHz
df_VLO/d_T	VLO frequency temperature drift	Measured at ACLK⁽¹⁾		0.2		%/°C
df_VLO/dV_CC	VLO frequency supply voltage drift	Measured at ACLK⁽²⁾		0.7		%/V
f_VLO,DC	Duty cycle	Measured at ACLK	40%	50%	60%

(1) Calculated using the box method: (MAX(–55°C to 95°C) – MIN(–55°C to 95°C)) / MIN(–55°C to 95°C) / (95°C – (–55°C))

(2) Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)

Table 4-8 lists the characteristics of the MODOSC.

Table 4-8 Module Oscillator (MODOSC)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
I_MODOSC	Current consumption	Enabled		25		μA
f_MODOSC	MODOSC frequency		4.0	4.8	5.4	MHz
f_MODOSC/dT	MODOSC frequency temperature drift⁽¹⁾			0.08		%/℃
f_MODOSC/dV_CC	MODOSC frequency supply voltage drift⁽²⁾			1.4		%/V
DC_MODOSC	Duty cycle	Measured at SMCLK, divide by 1	40%	50%	60%

(1) Calculated using the box method: (MAX(–55°C to 95°C) – MIN(–55°C to 95°C)) / MIN(–55°C to 95°C) / (95°C – (–55°C))

(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

4.13.4 Wake-up Characteristics

Table 4-9 lists the wake-up times.

Table 4-9 Wake-up Times From Low-Power Modes and Reset

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	TYP	MAX	UNIT
t_{WAKE-UP FRAM}	(Additional) wake-up time to activate the FRAM in AM if previously disabled by the FRAM controller or from an LPM if immediate activation is selected for wakeup			6	10	μs
t_{WAKE-UP LPM0}	Wake-up time from LPM0 to active mode⁽¹⁾		2.2 V, 3.0 V		400 + 1.5 / f_DCO	ns
t_{WAKE-UP LPM1}	Wake-up time from LPM1 to active mode⁽¹⁾		2.2 V, 3.0 V	6		μs
t_{WAKE-UP LPM2}	Wake-up time from LPM2 to active mode⁽¹⁾		2.2 V, 3.0 V	6		μs
t_{WAKE-UP LPM3}	Wake-up time from LPM3 to active mode⁽¹⁾		2.2 V, 3.0 V	7	10	μs
t_{WAKE-UP LPM4}	Wake-up time from LPM4 to active mode⁽¹⁾		2.2 V, 3.0 V	7	10	μs
t_{WAKE-UP LPM3.5}	Wake-up time from LPM3.5 to active mode⁽²⁾		2.2 V, 3.0 V	250	375	μs
t_{WAKE-UP LPM4.5}	Wake-up time from LPM4.5 to active mode⁽²⁾	SVSHE = 1	2.2 V, 3.0 V	250	375	μs
t_{WAKE-UP LPM4.5}	Wake-up time from LPM4.5 to active mode⁽²⁾	SVSHE = 0	2.2 V, 3.0 V	1	1.5	ms
t_WAKE-UP-RST	Wake-up time from a RST pin triggered reset to active mode⁽²⁾		2.2 V, 3.0 V	318	400	μs
t_WAKE-UP-BOR	Wake-up time from power-up to active mode ⁽²⁾		2.2 V, 3.0 V	1	1.5	ms

(1) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first externally observable MCLK clock edge. MCLK is sourced by the DCO and the MCLK divider is set to divide-by-1 (DIVMx = 000b, f_MCLK = f_DCO). This time includes the activation of the FRAM during wakeup.

(2) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first instruction of the user program is executed.

Table 4-10 lists the typical charge consumed during wakeup from various low-power modes.

Table 4-10 Typical Wake-up Charge⁽¹⁾

also see Figure 4-7 and Figure 4-8

PARAMETER		TEST CONDITIONS	TYP	UNIT
Q_{WAKE-UP FRAM}	Charge used for activating the FRAM in AM or during wake-up from LPM0 if previously disabled by the FRAM controller.		15.1	nAs
Q_{WAKE-UP LPM0}	Charge used for wake-up from LPM0 to active mode (with FRAM active)		4.4	nAs
Q_{WAKE-UP LPM1}	Charge used for wake-up from LPM1 to active mode (with FRAM active)		15.1	nAs
Q_{WAKE-UP LPM2}	Charge used for wake-up from LPM2 to active mode (with FRAM active)		15.3	nAs
Q_{WAKE-UP LPM3}	Charge used for wake-up from LPM3 to active mode (with FRAM active)		16.5	nAs
Q_{WAKE-UP LPM4}	Charge used for wake-up from LPM4 to active mode (with FRAM active)		16.5	nAs
Q_{WAKE-UP LPM3.5}	Charge used for wake-up from LPM3.5 to active mode⁽²⁾		76	nAs
Q_{WAKE-UP LPM4.5}	Charge used for wake-up from LPM4.5 to active mode⁽²⁾	SVSHE = 1	77	nAs
Q_{WAKE-UP LPM4.5}	Charge used for wake-up from LPM4.5 to active mode⁽²⁾	SVSHE = 0	77.5	nAs
Q_{WAKE-UP-RESET}	Charge used for reset from RST or BOR event to active mode⁽²⁾		75	nAs

(1) Charge used during the wake-up time from a given low-power mode to active mode. This does not include the energy required in active mode (for example, for an interrupt service routine).

(2) Charge required until start of user code. This does not include the energy required to reconfigure the device.

4.13.4.1 Typical Characteristics, Average LPM Currents vs Wake-up Frequency

MSP430FR5989-EP C001_wakeup25degC_slas789.gif

NOTE:

The average wake-up current does not include the energy required in active mode; for example, for an interrupt service routine or to reconfigure the device.

Figure 4-7 Average LPM Currents vs Wake-up Frequency at 25°C

MSP430FR5989-EP C002_wakeup85degC_slas789.gif

NOTE:

The average wake-up current does not include the energy required in active mode; for example, for an interrupt service routine or to reconfigure the device.

Figure 4-8 Average LPM Currents vs Wake-up Frequency at 95°C

4.13.5 Peripherals

4.13.5.1 Digital I/Os

Table 4-11 lists the characteristics of the digital inputs.

Table 4-11 Digital Inputs

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
V_IT+	Positive-going input threshold voltage		2.2 V	1.2		1.65	V
V_IT+	Positive-going input threshold voltage		3.0 V	1.65		2.25	V
V_IT–	Negative-going input threshold voltage		2.2 V	0.55		1.00	V
V_IT–	Negative-going input threshold voltage		3.0 V	0.75		1.35	V
V_hys	Input voltage hysteresis (V_IT+ – V_IT–)		2.2 V	0.44		0.98	V
V_hys	Input voltage hysteresis (V_IT+ – V_IT–)		3.0 V	0.60		1.30	V
R_Pull	Pullup or pulldown resistor	For pullup: V_IN = V_SS For pulldown: V_IN = V_CC		20	35	50	kΩ
C_I,dig	Input capacitance, digital only port pins	V_IN = V_SS or V_CC			3		pF
C_I,ana	Input capacitance, port pins with shared analog functions⁽¹⁾	V_IN = V_SS or V_CC			5		pF
I_lkg(Px.y)	High-impedance input leakage current	See ⁽²⁾ ⁽³⁾	2.2 V, 3.0 V	–20		+20	nA
t_(int)	External interrupt timing (external trigger pulse duration to set interrupt flag)⁽⁴⁾	Ports with interrupt capability (see and Section 3.2)	2.2 V, 3.0 V	20			ns
t_(RST)	External reset pulse duration on RST⁽⁵⁾		2.2 V, 3.0 V	2			µs

(1) If the port pins PJ.4/LFXIN and PJ.5/LFXOUT are used as digital I/Os, they are connected by a 4-pF capacitor and a 35-MΩ resistor in series. At frequencies of approximately 1 kHz and lower, the 4-pF capacitor can add to the pin capacitance of PJ.4/LFXIN and/or PJ.5/LFXOUT.

(2) The input leakage current is measured with V_SS or V_CC applied to the corresponding pins, unless otherwise noted.

(3) The input leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is disabled.

(4) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t_(int) is met. It may be set by trigger signals shorter than t_(int).

(5) Not applicable if RST/NMI pin configured as NMI.

Table 4-12 lists the characteristics of the digital outputs.

Table 4-12 Digital Outputs

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_(OHmax) = –1 mA⁽¹⁾	2.2 V	V_CC – 0.25		V_CC	V
		I_(OHmax) = –3 mA⁽²⁾	2.2 V	V_CC – 0.60		V_CC
		I_(OHmax) = –2 mA⁽¹⁾	3.0 V	V_CC – 0.25		V_CC
		I_(OHmax) = –6 mA⁽²⁾	3.0 V	V_CC – 0.60		V_CC
V_OL	Low-level output voltage	I_(OLmax) = 1 mA⁽¹⁾	2.2 V	V_SS		V_SS + 0.25	V
		I_(OLmax) = 3 mA⁽²⁾	2.2 V	V_SS		V_SS + 0.60
		I_(OLmax) = 2 mA⁽¹⁾	3.0 V	V_SS		V_SS + 0.25
		I_(OLmax) = 6 mA⁽²⁾	3.0 V	V_SS		V_SS + 0.60
f_Px.y	Port output frequency (with load)⁽⁵⁾	C_L = 20 pF, R_L ⁽³⁾ ⁽⁴⁾	2.2 V	16			MHz
f_Px.y	Port output frequency (with load)⁽⁵⁾	C_L = 20 pF, R_L ⁽³⁾ ⁽⁴⁾	3.0 V	16			MHz
f_{Port_CLK}	Clock output frequency⁽⁵⁾	ACLK, MCLK, or SMCLK at configured output port C_L = 20 pF⁽⁴⁾	2.2 V	16			MHz
f_{Port_CLK}	Clock output frequency⁽⁵⁾		3.0 V	16			MHz
t_rise,dig	Port output rise time, digital only port pins	C_L = 20 pF	2.2 V		4	15	ns
t_rise,dig	Port output rise time, digital only port pins	C_L = 20 pF	3.0 V		3	15	ns
t_fall,dig	Port output fall time, digital only port pins	C_L = 20 pF	2.2 V		4	15	ns
t_fall,dig	Port output fall time, digital only port pins	C_L = 20 pF	3.0 V		3	15	ns
t_rise,ana	Port output rise time, port pins with shared analog functions	C_L = 20 pF	2.2 V		6	15	ns
t_rise,ana		C_L = 20 pF	3.0 V		4	15	ns
t_fall,ana	Port output fall time, port pins with shared analog functions	C_L = 20 pF	2.2 V		6	15	ns
t_fall,ana		C_L = 20 pF	3.0 V		4	15	ns

(1) The maximum total current, I_(OHmax) and I_(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified.

(2) The maximum total current, I_(OHmax) and I_(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage drop specified.

(3) A resistive divider with 2 × R1 and R1 = 1.6 kΩ between V_CC and V_SS is used as load. The output is connected to the center tap of the divider. C_L = 20 pF is connected from the output to V_SS.

(4) The output voltage reaches at least 10% and 90% V_CC at the specified toggle frequency.

(5) The port can output frequencies at least up to the specified limit - it might support higher frequencies.

4.13.5.1.1 Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V

MSP430FR5989-EP D005_typical_low_level_output_current_vs_low_level_output_voltage_2p2v_SLASEC9.gif

V_CC = 2.2 V

Figure 4-9 Typical Low-Level Output Current vs Low-Level Output Voltage

MSP430FR5989-EP D007_typical_high_level_output_current_vs_high_level_output_voltage_2p2v_SLASEC9.gif

V_CC = 2.2 V

Figure 4-11 Typical High-Level Output Current vs High-Level Output Voltage

MSP430FR5989-EP D006_typical_low_level_output_current_vs_low_level_output_voltage_3v_SLASEC9.gif

V_CC = 3.0 V

Figure 4-10 Typical Low-Level Output Current vs Low-Level Output Voltage

MSP430FR5989-EP D008_typical_high_level_output_current_vs_high_level_output_voltage_3v_SLASEC9.gif

V_CC = 3.0 V

Figure 4-12 Typical High-Level Output Current vs High-Level Output Voltage

Table 4-13 lists the frequencies of the pin oscillator.

Table 4-13 Pin-Oscillator Frequency, Ports Px

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted) (see Section 4.13.5.1.2)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
fo_Px.y	Pin-oscillator frequency	Px.y, C_L = 10 pF⁽¹⁾	3.0 V		1200		kHz
fo_Px.y	Pin-oscillator frequency	Px.y, C_L = 20 pF⁽¹⁾	3.0 V		650		kHz

(1) C_L is the external load capacitance connected from the output to V_SS and includes all parasitic effects such as PCB traces.

4.13.5.1.2 Typical Characteristics, Pin-Oscillator Frequency

MSP430FR5989-EP C001_pinosc2p2Vlog_slas789.gif

V_CC = 2.2 V

One output active at a time.

Figure 4-13 Typical Oscillation Frequency vs Load Capacitance

MSP430FR5989-EP C002_pinosc3Vlog_slas789.gif

V_CC = 3.0 V

One output active at a time.

Figure 4-14 Typical Oscillation Frequency vs Load Capacitance

4.13.5.2 Timer_A and Timer_B

Table 4-14 lists the characteristics of the Timer_A.

Table 4-14 Timer_A

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
f_TA	Timer_A input clock frequency	Internal: SMCLK or ACLK, External: TACLK, Duty cycle = 50% ±10%	2.2 V, 3.0 V			16	MHz
t_TA,cap	Timer_A capture timing	All capture inputs, minimum pulse duration required for capture	2.2 V, 3.0 V	20			ns

Table 4-15 lists the characteristics of the Timer_B.

Table 4-15 Timer_B

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
f_TB	Timer_B input clock frequency	Internal: SMCLK or ACLK, External: TBCLK, Duty cycle = 50% ±10%	2.2 V, 3.0 V			16	MHz
t_TB,cap	Timer_B capture timing	All capture inputs, minimum pulse duration required for capture	2.2 V, 3.0 V	20			ns

4.13.5.3 eUSCI

Table 4-16 lists the supported clock frequencies of the eUSCI in UART mode.

Table 4-16 eUSCI (UART Mode) Clock Frequency

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
f_eUSCI	eUSCI input clock frequency	Internal: SMCLK or ACLK, External: UCLK, Duty cycle = 50% ±10%		16	MHz
f_BITCLK	BITCLK clock frequency (equals baud rate in MBaud)			4	MHz

Table 4-17 lists the characteristics of the eUSCI in UART mode.

Table 4-17 eUSCI (UART Mode)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
t_t	UART receive deglitch time⁽¹⁾	UCGLITx = 0	2.2 V, 3.0 V	5	30	ns
		UCGLITx = 1		20	90
		UCGLITx = 2		35	160
		UCGLITx = 3		50	220

(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. Thus the selected deglitch time can limit the max. useable baud rate. To ensure that pulses are correctly recognized their width should exceed the maximum specification of the deglitch time.

Table 4-18 lists the supported clock frequencies of the eUSCI in SPI master mode.

Table 4-18 eUSCI (SPI Master Mode) Clock Frequency

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
f_eUSCI	eUSCI input clock frequency	Internal: SMCLK or ACLK, Duty cycle = 50% ±10%		16	MHz

Table 4-19 lists the characteristics of the eUSCI in SPI master mode.

Table 4-19 eUSCI (SPI Master Mode)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
t_STE,LEAD	STE lead time, STE active to clock	UCSTEM = 1, UCMODEx = 01 or 10		1			UCxCLK cycles
t_STE,LAG	STE lag time, last clock to STE inactive	UCSTEM = 1, UCMODEx = 01 or 10		1			UCxCLK cycles
t_STE,ACC	STE access time, STE active to SIMO data out	UCSTEM = 0, UCMODEx = 01 or 10	2.2 V, 3.0 V			60	ns
t_STE,DIS	STE disable time, STE inactive to SOMI high impedance	UCSTEM = 0, UCMODEx = 01 or 10	2.2 V, 3.0 V			80	ns
t_SU,MI	SOMI input data setup time		2.2 V	40			ns
t_SU,MI	SOMI input data setup time		3.0 V	40			ns
t_HD,MI	SOMI input data hold time		2.2 V	0			ns
t_HD,MI	SOMI input data hold time		3.0 V	0			ns
t_VALID,MO	SIMO output data valid time⁽²⁾	UCLK edge to SIMO valid, C_L = 20 pF	2.2 V			10	ns
t_VALID,MO	SIMO output data valid time⁽²⁾	UCLK edge to SIMO valid, C_L = 20 pF	3.0 V			10	ns
t_HD,MO	SIMO output data hold time⁽³⁾	C_L = 20 pF	2.2 V		0		ns
t_HD,MO	SIMO output data hold time⁽³⁾	C_L = 20 pF	3.0 V		0		ns

(1) f_UCxCLK = 1/2t_LO/HI with tL_O/HI = max(t_{VALID,MO(eUSCI)} + t_SU,SI(Slave), t_SU,MI(eUSCI) + t_{VALID,SO(Slave)}).
For the slave parameters t_SU,SI(Slave) and t_{VALID,SO(Slave)}, see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams in Figure 4-15 and Figure 4-16.

(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 4-15 and Figure 4-16.

Figure 4-15 SPI Master Mode, CKPH = 0

Figure 4-16 SPI Master Mode, CKPH = 1

Table 4-20 lists the characteristics of the eUSCI in SPI slave mode.

Table 4-20 eUSCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
t_STE,LEAD	STE lead time, STE active to clock		2.2 V	45		ns
t_STE,LEAD	STE lead time, STE active to clock		3.0 V	40		ns
t_STE,LAG	STE lag time, Last clock to STE inactive		2.2 V	2		ns
t_STE,LAG	STE lag time, Last clock to STE inactive		3.0 V	3		ns
t_STE,ACC	STE access time, STE active to SOMI data out		2.2 V		45	ns
t_STE,ACC	STE access time, STE active to SOMI data out		3.0 V		40	ns
t_STE,DIS	STE disable time, STE inactive to SOMI high impedance		2.2 V		50	ns
t_STE,DIS	STE disable time, STE inactive to SOMI high impedance		3.0 V		45	ns
t_SU,SI	SIMO input data setup time		2.2 V	4		ns
t_SU,SI	SIMO input data setup time		3.0 V	4		ns
t_HD,SI	SIMO input data hold time		2.2 V	7		ns
t_HD,SI	SIMO input data hold time		3.0 V	7		ns
t_VALID,SO	SOMI output data valid time⁽²⁾	UCLK edge to SOMI valid, C_L = 20 pF	2.2 V		35	ns
t_VALID,SO	SOMI output data valid time⁽²⁾	UCLK edge to SOMI valid, C_L = 20 pF	3.0 V		35	ns
t_HD,SO	SOMI output data hold time⁽³⁾	C_L = 20 pF	2.2 V	0		ns
t_HD,SO	SOMI output data hold time⁽³⁾	C_L = 20 pF	3.0 V	0		ns

(1) f_UCxCLK = 1/2t_LO/HI with tL_O/HI ≥ max(t_{VALID,MO(Master)} + t_SU,SI(eUSCI), t_{SU,MI(Master)} + t_{VALID,SO(eUSCI)}).
For the master parameters t_{SU,MI(Master)} and t_{VALID,MO(Master)}, see the SPI parameters of the attached master.

(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams in Figure 4-17 and Figure 4-18.

(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams inFigure 4-17 and Figure 4-18.

Figure 4-17 SPI Slave Mode, CKPH = 0

Figure 4-18 SPI Slave Mode, CKPH = 1

Table 4-21 lists the characteristics of the eUSCI in I²C mode.

Table 4-21 eUSCI (I²C Mode)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted) (see Figure 4-19)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
f_eUSCI	eUSCI input clock frequency	Internal: SMCLK or ACLK, External: UCLK, Duty cycle = 50% ±10%				16	MHz
f_SCL	SCL clock frequency		2.2 V, 3.0 V	0		400	kHz
t_HD,STA	Hold time (repeated) START	f_SCL = 100 kHz	2.2 V, 3.0 V	4.0			µs
t_HD,STA	Hold time (repeated) START	f_SCL > 100 kHz	2.2 V, 3.0 V	0.6			µs
t_SU,STA	Setup time for a repeated START	f_SCL = 100 kHz	2.2 V, 3.0 V	4.7			µs
t_SU,STA	Setup time for a repeated START	f_SCL > 100 kHz	2.2 V, 3.0 V	0.6			µs
t_HD,DAT	Data hold time		2.2 V, 3.0 V	0			ns
t_SU,DAT	Data setup time		2.2 V, 3.0 V	100			ns
t_SU,STO	Setup time for STOP	f_SCL = 100 kHz	2.2 V, 3.0 V	4.0			µs
t_SU,STO	Setup time for STOP	f_SCL > 100 kHz	2.2 V, 3.0 V	0.6			µs
t_BUF	Bus free time between STOP and START conditions	f_SCL = 100 kHz		4.7			µs
t_BUF	Bus free time between STOP and START conditions	f_SCL > 100 kHz		1.3			µs
t_SP	Pulse duration of spikes suppressed by input filter	UCGLITx = 0	2.2 V, 3.0 V	50		250	ns
		UCGLITx = 1		25		125
		UCGLITx = 2		12.5		62.5
		UCGLITx = 3		6.3		31.5
t_TIMEOUT	Clock low time-out	UCCLTOx = 1	2.2 V, 3.0 V		27		ms
		UCCLTOx = 2			30
		UCCLTOx = 3			33

Figure 4-19 I²C Mode Timing

4.13.5.4 LCD Controller

Table 4-22 lists the operating conditions of the LCD_C.

Table 4-22 LCD_C, Recommended Operating Conditions

			MIN	NOM	MAX	UNIT
V_{CC,LCD_C,CP en,3.6}	Supply voltage range, charge pump enabled, V_LCD ≤ 3.6 V	LCDCPEN = 1, 0000b < VLCDx ≤ 1111b (charge pump enabled, V_LCD ≤ 3.6 V)	2.2		3.6	V
V_{CC,LCD_C,CP en,3.3}	Supply voltage range, charge pump enabled, V_LCD ≤ 3.3 V	LCDCPEN = 1, 0000b < VLCDx ≤ 1100b (charge pump enabled, V_LCD ≤ 3.3 V)	2.0		3.6	V
V_{CC,LCD_C,int. bias}	Supply voltage range, internal biasing, charge pump disabled	LCDCPEN = 0, VLCDEXT = 0	2.4		3.6	V
V_{CC,LCD_C,ext. bias}	Supply voltage range, external biasing, charge pump disabled	LCDCPEN = 0, VLCDEXT = 0	2.4		3.6	V
V_{CC,LCD_C,VLCDEXT}	Supply voltage range, external LCD voltage, internal or external biasing, charge pump disabled	LCDCPEN = 0, VLCDEXT = 1	2.0		3.6	V
V_LCDCAP	External LCD voltage at LCDCAP, internal or external biasing, charge pump disabled	LCDCPEN = 0, VLCDEXT = 1	2.4		3.6	V
C_LCDCAP	Capacitor value on LCDCAP when charge pump enabled	LCDCPEN = 1, VLCDx > 0000b (charge pump enabled)	4.7_-20%	4.7	10_+20%	µF
f_ACLK,in	ACLK input frequency range		30	32.768	40	kHz
f_LCD	LCD frequency range	f_FRAME = 1/(2 × mux) × f_LCD with mux = 1 (static) to 8	0		1024	Hz
f_FRAME,4mux	LCD frame frequency range	f_FRAME,4mux(MAX) = 1/(2 × 4) × f_LCD(MAX) = 1/(2 × 4) × 1024 Hz			128	Hz
f_FRAME,8mux	LCD frame frequency range	f_FRAME,8mux(MAX) = 1/(2 × 4) × f_LCD(MAX) = 1/(2 × 8) × 1024 Hz			64	Hz
C_Panel	Panel capacitance	f_LCD = 1024 Hz, all common lines equally loaded			10000	pF
V_R33	Analog input voltage at R33	LCDCPEN = 0, VLCDEXT = 1	2.4		V_CC+0.2	V
V_R23,1/3bias	Analog input voltage at R23	LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 0	V_R13	V_R03 + 2/3 × (V_R33-V_R03)	V_R33	V
V_R13,1/3bias	Analog input voltage at R13 with 1/3 biasing	LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 0	V_R03	V_R03 + 1/3 × (V_R33 – V_R03)	V_R23	V
V_R13,1/2bias	Analog input voltage at R13 with 1/2 biasing	LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 1	V_R03	V_R03 + 1/2 × (V_R33 – V_R03)	V_R33	V
V_R03	Analog input voltage at R03	R0EXT = 1	V_SS			V
V_LCD-V_R03	Voltage difference between V_LCD and R03	LCDCPEN = 0, R0EXT = 1	2.4		V_CC+0.2	V
V_LCDREF	External LCD reference voltage applied at LCDREF	VLCDREFx = 01	0.8	1.0	1.2	V

Table 4-23 lists the characteristics of the LCD_C.

Table 4-23 LCD_C Electrical Characteristics

over operating junction temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
V_LCD,0	LCD voltage	VLCDx = 0000, VLCDEXT = 0	2.4 V to 3.6 V		V_CC		V
V_LCD,1		LCDCPEN = 1, VLCDx = 0001b	2 V to 3.6 V	2.49	2.60	2.72
V_LCD,2		LCDCPEN = 1, VLCDx = 0010b	2 V to 3.6 V		2.66
V_LCD,3		LCDCPEN = 1, VLCDx = 0011b	2 V to 3.6 V		2.72
V_LCD,4		LCDCPEN = 1, VLCDx = 0100b	2 V to 3.6 V		2.78
V_LCD,5		LCDCPEN = 1, VLCDx = 0101b	2 V to 3.6 V		2.84
V_LCD,6		LCDCPEN = 1, VLCDx = 0110b	2 V to 3.6 V		2.90
V_LCD,7		LCDCPEN = 1, VLCDx = 0111b	2 V to 3.6 V		2.96
V_LCD,8		LCDCPEN = 1, VLCDx = 1000b	2 V to 3.6 V		3.02
V_LCD,9		LCDCPEN = 1, VLCDx = 1001b	2 V to 3.6 V		3.08
V_LCD,10		LCDCPEN = 1, VLCDx = 1010b	2 V to 3.6 V		3.14
V_LCD,11		LCDCPEN = 1, VLCDx = 1011b	2 V to 3.6 V		3.20
V_LCD,12		LCDCPEN = 1, VLCDx = 1100b	2 V to 3.6 V		3.26
V_LCD,13		LCDCPEN = 1, VLCDx = 1101b	2.2 V to 3.6 V		3.32
V_LCD,14		LCDCPEN = 1, VLCDx = 1110b	2.2 V to 3.6 V		3.38
V_LCD,15		LCDCPEN = 1, VLCDx = 1111b	2.2 V to 3.6 V	3.32	3.44	3.6
V_LCD,7,0.8	LCD voltage with external reference of 0.8 V	LCDCPEN = 1, VLCDx = 0111b, VLCDREFx = 01b, V_LCDREF = 0.8 V	2 V to 3.6 V		2.96 × 0.8 V		V
V_LCD,7,1.0	LCD voltage with external reference of 1.0 V	LCDCPEN = 1, VLCDx = 0111b, VLCDREFx = 01b, V_LCDREF = 1.0 V	2 V to 3.6 V		2.96 × 1.0 V		V
V_LCD,7,1.2	LCD voltage with external reference of 1.2 V	LCDCPEN = 1, VLCDx = 0111b, VLCDREFx = 01b, V_LCDREF = 1.2 V	2.2 V to 3.6 V		2.96 × 1.2 V		V
ΔV_LCD	Voltage difference between consecutive VLCDx settings	ΔV_LCD = V_LCD,x - V_LCD,x-1 with x = 0010b to 1111b		40	60	80	mV
I_CC,Peak,CP	Peak supply currents due to charge pump activities	LCDCPEN = 1, VLCDx = 1111b external, with decoupling capacitor on DVCC supply ≥ 1 µF	2.2 V		600		µA
t_LCD,CP,on	Time to charge C_LCD when discharged	C_LCD = 4.7 µF, LCDCPEN = 0→1, VLCDx = 1111b	2.2 V		100	500	ms
I_CP,Load	Maximum charge pump load current	LCDCPEN = 1, VLCDx = 1111b	2.2 V	50			µA
R_LCD,Seg	LCD driver output impedance, segment lines	LCDCPEN = 0, I_LOAD = ±10 µA	2.2 V			10	kΩ
R_LCD,COM	LCD driver output impedance, common lines	LCDCPEN = 0, I_LOAD = ±10 µA	2.2 V			10	kΩ

4.13.5.5 ADC

Table 4-24 lists the input requirements of the ADC.

Table 4-24 12-Bit ADC, Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	NOM	MAX	UNIT
V_(Ax)	Analog input voltage range⁽¹⁾	All ADC12 analog input pins Ax		0		AVCC	V
I_{(ADC12_B) single-ended mode}	Operating supply current into AVCC and DVCC terminals⁽²⁾ ⁽³⁾	f_ADC12CLK = MODCLK, ADC12ON = 1, ADC12PWRMD = 0, ADC12DIF = 0, REFON = 0, ADC12SHTx = 0, ADC12DIV = 0	3.0 V		145	199	µA
I_{(ADC12_B) single-ended mode}			2.2 V		140	190	µA
I_{(ADC12_B) differential mode}	Operating supply current into AVCC and DVCC terminals⁽²⁾ ⁽³⁾	f_ADC12CLK = MODCLK, ADC12ON = 1, ADC12PWRMD = 0, ADC12DIF = 1, REFON = 0, ADC12SHTx= 0, ADC12DIV = 0	3.0 V		175	245	µA
I_{(ADC12_B) differential mode}			2.2 V		170	230	µA
C_I	Input capacitance	Only one terminal Ax can be selected at one time	2.2 V		10	15	pF
R_I	Input MUX ON resistance	0 V ≤ V_(Ax) ≤ AVCC	>2 V		0.5	4	kΩ
R_I	Input MUX ON resistance	0 V ≤ V_(Ax) ≤ AVCC	<2 V		1	10	kΩ

(1) The analog input voltage range must be within the selected reference voltage range V_R+ to V_R– for valid conversion results.

(2) The internal reference supply current is not included in current consumption parameter I_{(ADC12_B)}.

(3) Approximately 60% (typical) of the total current into the AVCC and DVCC terminals is from AVCC.

Table 4-25 lists the timing parameters of the ADC.

Table 4-25 12-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
f_ADC12CLK	Frequency for specified performance	For specified performance of ADC12 linearity parameters with ADC12PWRMD = 0. If ADC12PWRMD = 1, the maximum is 1/4 of the value shown here.		0.45		5.4	MHz
f_ADC12CLK	Frequency for reduced performance	Linearity parameters have reduced performance			32.768		kHz
f_ADC12OSC	Internal oscillator⁽³⁾	ADC12DIV = 0, f_ADC12CLK = f_ADC12OSC from MODCLK		4	4.8	5.4	MHz
t_CONVERT	Conversion time	REFON = 0, Internal oscillator, f_ADC12CLK = f_ADC12OSC from MODCLK, ADC12WINC = 0		2.6		3.5	µs
t_CONVERT	Conversion time	External f_ADC12CLK from ACLK, MCLK, or SMCLK, ADC12SSEL ≠ 0			See ⁽²⁾		µs
t_ADC12ON	Turnon settling time of the ADC	See ⁽¹⁾			100		ns
t_ADC12OFF	Time ADC must be off before it can be turned on again	t_ADC12OFF must be met to make sure that t_ADC12ON time holds.			100		ns
t_Sample	Sampling time	R_S = 400 Ω, R_I = 4 kΩ, C_I = 15 pF, C_pext= 8 pF⁽⁴⁾	All pulse sample mode (ADC12SHP = 1) and extended sample mode (ADC12SHP = 0) with buffered reference (ADC12VRSEL = 0x1, 0x3, 0x5, 0x7, 0x9, 0xB, 0xD, 0xF)	1			µs
t_Sample	Sampling time	R_S = 400 Ω, R_I = 4 kΩ, C_I = 15 pF, C_pext= 8 pF⁽⁴⁾	Extended sample mode (ADC12SHP = 0) with unbuffered reference (ADC12VRSEL= 0x0, 0x2, 0x4, 0x6, 0xC, 0xE)	See ⁽⁵⁾			µs

(1) The condition is that the error in a conversion started after t_ADC12ON is less than ±0.5 LSB. The reference and input signal are already settled.

(2) 14 × 1 / f_ADC12CLK. If ADC12WINC = 1, then 15 × 1 / f_ADC12CLK.

(3) The ADC12OSC is sourced directly from MODOSC inside the UCS.

(4) Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB: t_sample = ln(2ⁿ⁺²) × (R_S + R_I) × (C_I + C_pext), R_S < 10 kΩ, where n = ADC resolution = 12, R_S = external source resistance, C_pext = external parasitic capacitance.

(5) 6 × 1 / f_ADC12CLK.

Table 4-26 lists the linearity parameters of the ADC when using an external reference.

Table 4-26 12-Bit ADC, Linearity Parameters With External Reference⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
Resolution	Number of no missing code output-code bits		12			bits
E_I	Integral linearity error (INL) for differential input	1.2 V ≤ V_R+ – V_R– ≤ AV_CC			±2.4	LSB
E_I	Integral linearity error (INL) for single ended inputs	1.2 V ≤ V_R+ – V_R– ≤ AV_CC			±2.8	LSB
E_D	Differential linearity error (DNL)		–0.99		+1.0	LSB
E_O	Offset error⁽²⁾ ⁽³⁾	ADC12VRSEL = 0x2 or 0x4 without TLV calibration, TLV calibration data can be used to improve the parameter⁽⁴⁾		±0.5	±1.5	mV
E_G,ext	Gain error	With external voltage reference without internal buffer (ADC12VRSEL = 0x2 or 0x4) without TLV calibration, TLV calibration data can be used to improve the parameter⁽⁴⁾, V_R+ = 2.5 V, V_R– = AVSS		±0.8	±2.5	LSB
E_G,ext	Gain error	With external voltage reference with internal buffer (ADC12VRSEL = 0x3), V_R+ = 2.5 V, V_R– = AVSS		±1		LSB
E_T,ext	Total unadjusted error	With external voltage reference without internal buffer (ADC12VRSEL = 0x2 or 0x4) without TLV calibration, TLV calibration data can be used to improve the parameter⁽⁴⁾, V_R+ = 2.5 V, V_R– = AVSS		±1.4	±4.7	LSB
E_T,ext	Total unadjusted error	With external voltage reference with internal buffer (ADC12VRSEL = 0x3), V_R+ = 2.5 V, V_R– = AVSS		±1.4		LSB

(1) See Table 4-28 and Table 4-34 for more information on internal reference performance, and see Designing With the MSP430FR59xx and MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal or external reference.

(2) Offset is measured as the input voltage (at which ADC output transitions from 0 to 1) minus 0.5 LSB.

(3) Offset increases as I_R drop increases when V_R– is AVSS.

(4) For details, see the device descriptor in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide.

Table 4-27 lists the dynamic performance characteristics of the ADC with differential inputs and an external reference.

Table 4-27 12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference⁽²⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
SNR	Signal-to-noise	V_R+ = 2.5 V, V_R– = AVSS			71		dB
ENOB	Effective number of bits⁽¹⁾	V_R+ = 2.5 V, V_R– = AVSS			11.2		bits

(1) ENOB = (SINAD – 1.76) / 6.02

(2) See Table 4-28 and Table 4-34 for more information on internal reference performance, and see Designing With the MSP430FR59xx and MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal or external reference.

Table 4-28 lists the dynamic performance characteristics of the ADC with differential inputs and an internal reference.

Table 4-28 12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
ENOB	Effective number of bits⁽²⁾	V_R+ = 2.5 V, V_R– = AVSS			10.7		Bits

(1) See Table 4-34 for more information on internal reference performance, and see Designing With the MSP430FR59xx and MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal or external reference.

(2) ENOB = (SINAD – 1.76) / 6.02

Table 4-29 lists the dynamic performance characteristics of the ADC with single-ended inputs and an external reference.

Table 4-29 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SNR	Signal-to-noise	V_R+ = 2.5 V, V_R– = AVSS		68		dB
ENOB	Effective number of bits⁽²⁾	V_R+ = 2.5 V, V_R– = AVSS		10.7		bits

(1) See Table 4-30 and Table 4-34 for more information on internal reference performance, and see Designing With the MSP430FR59xx and MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal or external reference.

(2) ENOB = (SINAD – 1.76) / 6.02

Table 4-30 lists the dynamic performance characteristics of the ADC with single-ended inputs and an internal reference.

Table 4-30 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ENOB	Effective number of bits⁽²⁾	V_R+ = 2.5 V, V_R– = AVSS		10.4		bits

(2) ENOB = (SINAD – 1.76) / 6.02

Table 4-31 lists the dynamic performance characteristics of the ADC using a 32.678-kHz clock.

Table 4-31 12-Bit ADC, Dynamic Performance With 32.768-kHz Clock

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		TYP	UNIT
ENOB	Effective number of bits⁽¹⁾	Reduced performance with f_ADC12CLK from ACLK LFXT 32.768 kHz, V_R+ = 2.5 V, V_R– = AVSS		10	bits

(1) ENOB = (SINAD – 1.76) / 6.02

Table 4-32 lists the characteristics of the temperature sensor and built-in V_1/2 of the ADC.

Table 4-32 12-Bit ADC, Temperature Sensor and Built-In V_1/2

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_SENSOR	See ⁽¹⁾ ⁽²⁾ (also see Figure 4-20)	ADC12ON = 1, ADC12TCMAP = 1, T_A = 0°C		700		mV
TC_SENSOR	See ⁽²⁾	ADC12ON = 1, ADC12TCMAP = 1		2.5		mV/°C
t_{SENSOR(sample)}	Sample time required if ADCTCMAP = 1 and channel (MAX – 1) is selected⁽³⁾	ADC12ON = 1, ADC12TCMAP = 1, Error of conversion result ≤ 1 LSB	30			µs
V_1/2	AVCC voltage divider for ADC12BATMAP = 1 on MAX input channel	ADC12ON = 1, ADC12BATMAP = 1	47.5%	50%	52.5%
I_{V 1/2}	Current for battery monitor during sample time	ADC12ON = 1, ADC12BATMAP = 1		38	63	µA
t_{V 1/2 (sample)}	Sample time required if ADC12BATMAP = 1 and channel MAX is selected⁽⁴⁾	ADC12ON = 1, ADC12BATMAP = 1	1.7			µs

(1) The temperature sensor offset can be as much as ±30°C. TI recommends a single-point calibration to minimize the offset error of the built-in temperature sensor.

(2) The device descriptor structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each available reference voltage level. The sensor voltage can be computed as V_SENSE = TC_SENSOR × (Temperature, °C) + V_SENSOR, where TC_SENSOR and V_SENSOR can be computed from the calibration values for higher accuracy.

(3) The typical equivalent impedance of the sensor is 250 kΩ. The sample time required includes the sensor-on time t_SENSOR(on).

(4) The on-time t_V1/2(on) is included in the sampling time t_V1/2(sample); no additional on time is needed.

MSP430FR5989-EP slau367adc12b_vtemp_vs_temp.gif

Figure 4-20 Typical Temperature Sensor Voltage

Table 4-33 lists the external reference requirements for the ADC.

Table 4-33 12-Bit ADC, External Reference⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_R+	Positive external reference voltage input VeREF+ or VeREF- based on ADC12VRSEL bit	V_R+ > V_R–	1.2		AV_CC	V
V_R–	Negative external reference voltage input VeREF+ or VeREF- based on ADC12VRSEL bit	V_R+ > V_R–	0		1.2	V
V_R+ – V_R–	Differential external reference voltage input	V_R+ > V_R–	1.2		AV_CC	V
I_VeREF+, I_VeREF-	Static input current, singled-ended input mode	1.2 V ≤ V_eREF+ ≤ V_AVCC, V_eREF– = 0 V f_ADC12CLK = 5 MHz, ADC12SHTx = 1h, ADC12DIF = 0, ADC12PWRMD = 0			±10	µA
I_VeREF+, I_VeREF-	Static input current, singled-ended input mode	1.2 V ≤ V_eREF+ ≤ V_AVCC , V_eREF– = 0 V f_ADC12CLK = 5 MHz, ADC12SHTx = 8h, ADC12DIF = 0, ADC12PWRMD = 01			±2.5	µA
I_VeREF+, I_VeREF-	Static input current, differential input mode	1.2 V ≤ V_eREF+ ≤ V_AVCC, V_eREF– = 0 V f_ADC12CLK = 5 MHz, ADC12SHTx = 1h, ADC12DIF = 1, ADC12PWRMD = 0			±20	µA
I_VeREF+, I_VeREF-	Static input current, differential input mode	1.2 V ≤ V_eREF+ ≤ V_AVCC , V_eREF– = 0 V f_ADC12CLK = 5 MHz, ADC12SHTx = 8h, ADC12DIF = 1, ADC12PWRMD = 1			±5	µA
I_VeREF+	Peak input current with single-ended input	0 V ≤ V_eREF+ ≤ V_AVCC, ADC12DIF = 0		1.5		mA
I_VeREF+	Peak input current with differential input	0 V ≤ V_eREF+ ≤ V_AVCC, ADC12DIF = 1		3		mA
C_VeREF+/-	Capacitance at VeREF+ or VeREF- terminal	See ⁽²⁾	10			µF

(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, C_I, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.

(2) Connect two decoupling capacitors, 10 µF and 470 nF, to VeREF to decouple the dynamic current required for an external reference source if it is used for the ADC12_B. Also see the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide.

4.13.5.6 Reference

Table 4-34 lists the characteristics of the built-in voltage reference.

Table 4-34 REF, Built-In Reference

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
V_REF+	Positive built-in reference voltage output	REFVSEL = {2} for 2.5 V, REFON = 1	2.7 V		2.5	±1.5%	V
		REFVSEL = {1} for 2.0 V, REFON = 1	2.2 V		2.0	±1.5%
		REFVSEL = {0} for 1.2 V, REFON = 1	1.8 V		1.2	±1.8%
Noise	RMS noise at VREF⁽³⁾	From 0.1 Hz to 10 Hz, REFVSEL = {0}			110		µV
V_{OS_BUF_INT}	VREF ADC BUF_INT buffer offset⁽⁴⁾	T_J = 25°C , ADC ON, REFVSEL = {0}, REFON = 1, REFOUT = 0		–12		+12	mV
V_{OS_BUF_EXT}	VREF ADC BUF_EXT buffer offset⁽⁴⁾	T_J = 25°C, REFVSEL = {0} , REFOUT = 1, REFON = 1 or ADC ON		–12		+12	mV
AV_CC(min)	AVCC minimum voltage, Positive built-in reference active	REFVSEL = {0} for 1.2 V		1.8			V
		REFVSEL = {1} for 2.0 V		2.2
		REFVSEL = {2} for 2.5 V		2.7
I_REF+	Operating supply current into AVCC terminal⁽¹⁾	REFON = 1	3 V		8	15	µA
I_{REF+_ADC_BUF}	Operating supply current into AVCC terminal⁽¹⁾	ADC ON, REFOUT = 0, REFVSEL = {0, 1, 2}, ADC12PWRMD = 0,	3 V		225	355	µA
		ADC ON, REFOUT = 1, REFVSEL = {0, 1, 2}, ADC12PWRMD = 0	3 V		1030	1660
		ADC ON, REFOUT = 0, REFVSEL = {0, 1, 2}, ADC12PWRMD = 1	3 V		120	185
		ADC ON, REFOUT = 1, REFVSEL = {0, 1, 2}, ADC12PWRMD = 1	3 V		545	895
		ADC OFF, REFON = 1, REFOUT = 1, REFVSEL = {0, 1, 2}	3 V		1085
I_O(VREF+)	VREF maximum load current, VREF+ terminal	REFVSEL = {0, 1, 2}, AVCC = AVCC(min) for each reference level, REFON = REFOUT = 1		–1000		+10	µA
ΔVout/ΔIo (VREF+)	Load-current regulation, VREF+ terminal	REFVSEL = {0, 1, 2}, I_O(VREF+) = +10 µA or –1000 µA, AV_CC = AV_CC(min) for each reference level, REFON = REFOUT = 1				2500	µV/mA
C_VREF+/-	Capacitance at VREF+ and VREF- terminals	REFON = REFOUT = 1		0		100	pF
TC_REF+	Temperature coefficient of built-in reference	REFVSEL = {0, 1, 2}, REFON = REFOUT = 1, T_A = –55°C to 95°C⁽⁵⁾			18	50	ppm/K
PSRR_DC	Power supply rejection ratio (DC)	AV_CC = AV_CC_(min) to AV_CC(max), T_J = 25°C, REFVSEL = {0, 1, 2}, REFON = REFOUT = 1			120	400	µV/V
PSRR_AC	Power supply rejection ratio (AC)	dAV_CC= 0.1 V at 1 kHz			3.0		mV/V
t_SETTLE	Settling time of reference voltage⁽²⁾	AV_CC = AV_CC _(min) to AV_CC(max), REFVSEL = {0, 1, 2}, REFON = 0 → 1			75	80	µs

(1) The internal reference current is supplied through terminal AVCC.

(2) The condition is that the error in a conversion started after t_REFON is less than ±0.5 LSB.

(3) Internal reference noise affects ADC performance when ADC uses internal reference. See Designing With the MSP430FR59xx and MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal versus external reference.

(4) Buffer offset affects ADC gain error and thus total unadjusted error.

(5) Calculated using the box method: (MAX(–55°C to 95°C) – MIN(–55°C to 95°C)) / MIN(–55°C to 95°C)/(95°C – (–55°C)).

4.13.5.7 Comparator

Table 4-35 lists the characteristics of the comparator.

Table 4-35 Comparator_E

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
I_{AVCC_COMP}	Comparator operating supply current into AVCC, excludes reference resistor ladder	CEPWRMD = 00, CEON = 1, CERSx = 00 (fast)	2.2 V, 3.0 V		11	20	µA
		CEPWRMD = 01, CEON = 1, CERSx = 00 (medium)			9	17
		CEPWRMD = 10, CEON = 1, CERSx = 00 (slow), T_J = 30°C				0.6
		CEPWRMD = 10, CEON = 1, CERSx = 00 (slow), T_J = 95°C				1.3
I_{AVCC_REF}	Quiescent current of resistor ladder into AVCC, including REF module current	CEREFLx = 01, CERSx = 10, REFON = 0, CEON = 0, CEREFACC = 0	2.2 V, 3.0 V		12	15	µA
I_{AVCC_REF}		CEREFLx = 01, CERSx = 10, REFON = 0, CEON = 0, CEREFACC = 1	2.2 V, 3.0 V		5	7	µA
V_REF	Reference voltage level	CERSx = 11, CEREFLx = 01, CEREFACC = 0	1.8 V	1.17	1.2	1.23	V
		CERSx = 11, CEREFLx = 10, CEREFACC = 0	2.2 V	1.92	2.0	2.08
		CERSx = 11, CEREFLx = 11, CEREFACC = 0	2.7 V	2.40	2.5	2.60
		CERSx = 11, CEREFLx = 01, CEREFACC = 1	1.8 V	1.10	1.2	1.245
		CERSx = 11, CEREFLx = 10, CEREFACC = 1	2.2 V	1.90	2.0	2.08
		CERSx = 11, CEREFLx = 11, CEREFACC = 1	2.7 V	2.35	2.5	2.60
V_IC	Common-mode input range			0		V_CC-1	V
V_OFFSET	Input offset voltage	CEPWRMD = 00		–32		32	mV
		CEPWRMD = 01		–32		32
		CEPWRMD = 10		–30		30
C_IN	Input capacitance	CEPWRMD = 00 or CEPWRMD = 01			9		pF
C_IN	Input capacitance	CEPWRMD = 10			9		pF
R_SIN	Series input resistance	On (switch closed)			1	3	kΩ
R_SIN	Series input resistance	Off (switch open)		50			MΩ
t_PD	Propagation delay, response time	CEPWRMD = 00, CEF = 0, Overdrive ≥ 20 mV			260	330	ns
		CEPWRMD = 01, CEF = 0, Overdrive ≥ 20 mV			350	460	ns
		CEPWRMD = 10, CEF = 0, Overdrive ≥ 20 mV				15	µs
t_PD,filter	Propagation delay with filter active	CEPWRMD = 00 or 01, CEF = 1, Overdrive ≥ 20 mV, CEFDLY = 00			700	1000	ns
		CEPWRMD = 00 or 01, CEF = 1, Overdrive ≥ 20 mV, CEFDLY = 01			1.0	1.8	µs
		CEPWRMD = 00 or 01, CEF = 1, Overdrive ≥ 20 mV, CEFDLY = 10			2.0	3.5
		CEPWRMD = 00 or 01, CEF = 1, Overdrive ≥ 20 mV, CEFDLY = 11			4.0	7.0
t_{EN_CMP}	Comparator enable time	CEON = 0 → 1, VIN+, VIN- from pins, Overdrive ≥ 20 mV, CEPWRMD = 00			0.9	1.5	µs
		CEON = 0 → 1, VIN+, VIN- from pins, Overdrive ≥ 20 mV, CEPWRMD = 01			0.9	1.5
		CEON = 0 → 1, VIN+, VIN- from pins, Overdrive ≥ 20 mV, CEPWRMD = 10			15	100
t_{EN_CMP_VREF}	Comparator and reference ladder and reference voltage enable time	CEON = 0 → 1, CEREFLX = 10, CERSx = 10 or 11, CEREF0 = CEREF1 = 0x0F, Overdrive ≥ 20 mV			350	1500	µs
V_{CE_REF}	Reference voltage for a given tap	VIN = reference into resistor ladder, n = 0 to 31		VIN × (n + 0.5) / 32	VIN × (n + 1) / 32	VIN × (n + 1.5) / 32	V

4.13.5.8 Scan Interface

Table 4-36 lists the port timing characteristics of the ESI.

Table 4-36 Extended Scan Interface, Port Drive, Port Timing

over recommended operating junction temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
V_OL(ESICHx)	Voltage drop due to ON-resistance of excitation transistor (see Figure 4-21)	I(ESICHx) = 2 mA, ESITEN = 1	3 V		0.3	V
V_OH(ESICHx)	Voltage drop due to ON-resistance of damping transistor⁽¹⁾ (see Figure 4-21)	I_(ESICHx) = –200 µA, ESITEN = 1	3 V		0.1	V
V_OL(ESICOM)		I_(ESICOM) = 3 mA, ESISH = 1	2.2 V, 3 V	0	0.1	V
I_{ESICHx(tri-state)}		V_(ESICHx) = 0 V to AV_CC, port function disabled, ESISH = 1	3 V	–50	50	nA

(1) ESICOM = 1.5 V, supplied externally (see Figure 4-22).

MSP430FR5989-EP slas789_ESI_p6x_sifchx_timing.gif

Figure 4-21 P6.x/ESICHx Timing, ESICHx Function Selected

MSP430FR5989-EP slas789_ESI_vdrop_due_ron.gif

Figure 4-22 Voltage Drop Due to ON-Resistance

Table 4-37 lists the sample timing of the ESI.

Table 4-37 Extended Scan Interface, Sample Capacitor/Ri Timing ⁽²⁾

over operating junction temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	TYP	UNIT
C_SHC(ESICHx)	Sample capacitance on selected ESICHx pin	ESIEx(tsm) = 1, ESISH = 1	2.2 V, 3 V	7	pF
Ri_(ESICHx)	Serial input resistance at the ESICHx pin	ESIEx(tsm) = 1, ESISH = 1	2.2 V, 3 V	1.5	kΩ
t_Hold	Maximum hold time⁽¹⁾	ESISHTSM⁽³⁾ = 1, measurement sequence uses at least two ESICHx inputs, ΔV_sample < 3 mV		62	µs

(1) The sampled voltage at the sample capacitance varies less than 3 mV (ΔV_sample) during the hold time t_Hold. If the voltage is sampled after t_Hold, the sampled voltage may be any other value.

(2) The minimum sampling time (7.6 tau for 1/2 LSB accuracy) with maximum C_SHC(ESICHx) and Ri_(ESICHx) and Ri_(source) is t_sample(min) ≈ 7.6 × C_SHC(ESICHx) × (Ri_(ESICHx) + Ri_(source)) with Ri_(source) estimated at 3 kΩ, t_sample(min) = 319 ns.

(3) The control bit ESIVSS was renamed to ESISHTSM to avoid confusion with supply pin naming.

Table 4-38 lists the characteristics of the ESI V_CC/2 generator.

Table 4-38 Extended Scan Interface, V_CC/2 Generator

over operating junction temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
V_CC	ESI V_CC/2 generator supply voltage	AVCC = DVCC = ESIDVCC (connected together), AVSS = DVSS = ESIDVSS (connected together)		2.2		3.6	V
I_VMID	ESI V_CC/2 generator quiescent current	C_L at ESICOM pin = 470 nF ±20%, f_{refresh(ESICOM)} = 32768 Hz, T = 0°C to 95°C, R_ext = 1k in series to C_L	2.2 V, 3 V		370	500	nA
I_VMID	ESI V_CC/2 generator quiescent current	C_L at ESICOM pin = 470 nF ±20%, f_{refresh(ESICOM)} = 32768 Hz, T = –55°C to 95°C	2.2 V, 3 V		370	1600	nA
f_{refresh(ESICOM)}	V_CC/2 refresh frequency	Source clock = ACLK	2.2 V, 3 V		32.768		kHz
V_(ESICOM)	Output voltage at pin ESICOM	C_L at ESICOM pin = 470 nF ±20%, I_Load = 1 µA		AV_CC / 2 –0.07	AV_CC / 2	AV_CC / 2 + 0.07	V
t_on(ESICOM)	Time to reach 98% after V_CC / 2 is switched on	C_L at ESICOM pin = 470 nF ±20%, f_{refresh(ESICOM)} = 32768 Hz	2.2 V, 3 V		1.7	6	ms
t_{VccSettle (ESICOM)}	Settling time to ±V_CC / 2560 (2 LSB) after AV_CC voltage change	ESIEN = 1, ESIVMIDEN⁽¹⁾ = 1, ESISH = 0, AV_CC = AV_CC –100 mV, f_{refresh(ESICOM)} = 32768 Hz	2.2 V, 3 V		3		ms
t_{VccSettle (ESICOM)}		AV_CC = AV_CC + 100 mV, f_{refresh(ESICOM)} = 32768 Hz	2.2 V, 3 V		3		ms

(1) The control bit ESIVCC2 was renamed to ESIVMIDEN to avoid confusion with supply pin naming.

Table 4-39 lists the characteristics of the ESI DAC.

Table 4-39 Extended Scan Interface, 12-Bit DAC

over operating junction temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
V_CC	ESI DAC supply voltage	ESIDVCC = AVCC = DVCC (connected together), ESIDVSS = AVSS = DVSS (connected together)		2.2		3.6	V
I_CC	ESI 12-bit DAC operating supply current into AVCC terminal ⁽¹⁾		2.2 V		10	27	µA
I_CC			3 V		14	35	µA
	Resolution				12		bit
INL	Integral nonlinearity	R_L = 1000 MΩ, C_L = 20 pF With autozeroing	2.2 V, 3 V	–10	±2	+10	LSB
DNL	Differential nonlinearity	R_L = 1000 MΩ, C_L = 20 pF, Without autozeroing	2.2 V, 3 V	–10		+10	LSB
DNL	Differential nonlinearity	R_L = 1000 MΩ, C_L = 20 pF, With autozeroing	2.2 V, 3 V	–10		+10	LSB
E_OS	Offset error	With autozeroing	2.2 V, 3 V		0		V
E_G	Gain error	With autozeroing	2.2 V, 3 V			0.6%
t_on(ESIDAC)	On time after AV_CC of ESIDAC is switched on	V_+ESICA – V_ESIDAC = ±6 mV	2.2 V, 3 V		2		µs
t_{Settle(ESIDAC)}	Settling time	ESIDAC code = 0h → A0h	2.2 V, 3 V		2		µs
t_{Settle(ESIDAC)}	Settling time	ESIDAC code = A0h → 0h	2.2 V, 3 V		2		µs

(1) This parameter covers one ESI 12-bit DAC, either ESI AFE1 12-bit DAC or ESI AFE2 12-bit DAC.

Table 4-40 lists the characteristics of the ESI comparator.

Table 4-40 Extended Scan Interface, Comparator

over operating junction temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
V_CC	ESI comparator supply voltage	ESIDVCC = AVCC = DVCC (connected together), ESIDVSS = AVSS = DVSS (connected together)		2.2		3.6	V
I_CC	ESI comparator operating supply current into AVCC terminal ⁽²⁾		2.2 V, 3 V		25	42	µA
V_IC	Common-mode input voltage range ⁽¹⁾		2.2 V, 3 V	0		V_CC – 1	V
V_Offset	Input offset voltage	After autozeroing	2.2 V, 3 V	–1.5		1.5	mV
dV_Offset/dT	Temperature coefficient of V_Offset ⁽³⁾	Without autozeroing	2.2 V, 3 V		40		µV/°C
dV_Offset/dT	Temperature coefficient of V_Offset ⁽³⁾	After autozeroing	2.2 V, 3 V		2		µV/°C
dV_Offset/dV_CC	V_Offset supply voltage (V_CC) sensitivity⁽⁴⁾	Without autozeroing			0.3		mV/V
dV_Offset/dV_CC	V_Offset supply voltage (V_CC) sensitivity⁽⁴⁾	After autozeroing			0.2		mV/V
V_hys	Input voltage hysteresis	V+ terminal = V- terminal = 0.5 × V_CC	2.2 V, 3 V		0.5		LSB
t_on(ESICA)	On time after ESICA is switched on	V_+ESICA – V_ESIDAC = +6 mV, V_+ESICA = 0.5 × AV_CC	2.2 V, 3 V		2.0		µs
t_{Settle(ESICA)}	Settle time	V_+ESICA – V_ESIDAC = –12 mV → 6 mV, V_+ESICA = 0.5 × AV_CC	2.2 V, 3 V		3.0		µs
t_autozero	Autozeroing time of comparator	V_input = V_CC / 2, \|V_offset\| < 1 mV	2.2 V, 3 V		3.0		µs

(1) The comparator output is reliable when at least one of the input signals is within the common-mode input voltage range.

(2) This parameter covers one single ESI comparator; either ESI AFE1 comparator or ESI AFE2 comparator.

(3) Calculated using the box method: (MAX(–55°C to 95°C) – MIN(–55°C to 95°C)) / MIN(–55°C to 95°C) / (95°C – (–55°C))

(4) Calculated using the box method: ABS((Voffset_Vcc_max – Voffset_Vcc_min)/(Vcc_max – Vcc_min))

Table 4-41 lists the characteristics of the ESI oscillator and clock.

Table 4-41 Extended Scan Interface, ESICLK Oscillator and TSM Clock Signals

over operating junction temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
V_CC	ESI oscillator supply voltage	ESIDVCC = AVCC = DVCC (connected together), ESIDVSS = AVSS = DVSS (connected together)		2.2		3.6	V
I_CC	ESI oscillator operating supply current	f_ESIOSC= 4.8 MHz, ESIDIV1x = 00b, ESICLKGON = 1, ESIEN = 1, no TSM sequence running	2.2 V		45		µA
I_CC	ESI oscillator operating supply current		3 V		50		µA
f_{ESIOSC_min}	ESI oscillator at minimum setting	T_J = 30°C, ESICLKFQ = 000000			2.3		MHz
f_{ESIOSC_max}	ESI oscillator at maximum setting	T_J = 30°C, ESICLKFQ = 111111			7.9		MHz
t_on(ESIOSC)	Start-up time including synchronization cycles	f_ESIOSC = 4.8 MHz	2.2 V, 3 V		400		ns
f_ESIOSC/dT	ESIOSC frequency temperature drift⁽¹⁾	f_ESIOSC= 4.8 MHz	2.2 V, 3 V		0.15		%/°C
f_ESIOSC/dV_CC	ESIOSC frequency supply voltage drift ⁽²⁾	f_ESIOSC= 4.8 MHz	2.2 V, 3 V		2		%/V
f_ESILFCLK	TSM low-frequency state clock				32.768	50	kHz
f_ESIHFCLK	TSM high-frequency state clock			0.25		8	MHz

(1) Calculated using the box method: (MAX(–55°C to 95°C) – MIN(–55°C to 95°C)) / MIN(–55°C to 95°C) / (95°C – (–55°C))

(2) Calculated using the box method: (MAX(2.2 V to 3.6 V) – MIN(2.2 V to 3.6 V)) / MIN(2.2 V to 3.6 V) / (3.6 V – 2.2 V)

4.13.5.9 FRAM Controller

Table 4-42 lists the characteristics of the FRAM.

Table 4-42 FRAM

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	UNIT
	Read and write endurance		10¹⁵		cycles
t_Retention	Data retention duration	T_J = 25°C	100		years
		T_J = 70°C	40
		T_J = 95°C	10
I_WRITE	Current to write into FRAM			I_READ⁽¹⁾	nA
I_ERASE	Erase current			n/a⁽²⁾	nA
t_WRITE	Write time			t_READ⁽³⁾	ns
t_READ	Read time	NWAITSx = 0		1 / f_SYSTEM⁽⁴⁾	ns
t_READ	Read time	NWAITSx = 1		2 / f_SYSTEM⁽⁴⁾	ns

(1) Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read current I_READ is included in the active mode current consumption numbers I_AM,FRAM.

(2) FRAM does not require a special erase sequence.

(3) Writing into FRAM is as fast as reading.

(4) The maximum read (and write) speed is specified by f_SYSTEM using the appropriate wait state settings (NWAITSx).

4.13.6 Emulation and Debug

Table 4-43 lists the characteristics of the JTAG and Spy-Bi-Wire interface.

Table 4-43 JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
I_JTAG	Supply current adder when JTAG active (but not clocked)	2.2 V, 3.0 V		40	100	μA
f_SBW	Spy-Bi-Wire input frequency	2.2 V, 3.0 V	0		10	MHz
t_SBW,Low	Spy-Bi-Wire low clock pulse duration	2.2 V, 3.0 V	0.04		15	μs
t_{SBW, En}	Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)⁽¹⁾	2.2 V, 3.0 V			110	μs
t_SBW,Rst	Spy-Bi-Wire return to normal operation time		15		100	μs
f_TCK	TCK input frequency, 4-wire JTAG⁽²⁾	2.2 V	0		16	MHz
f_TCK	TCK input frequency, 4-wire JTAG⁽²⁾	3.0 V	0		16	MHz
R_internal	Internal pulldown resistance on TEST	2.2 V, 3.0 V	20	35	50	kΩ
f_TCLK	TCLK/MCLK frequency during JTAG access, no FRAM access (limited by f_SYSTEM)				16	MHz
t_{TCLK,Low/High}	TCLK low or high clock pulse duration, no FRAM access				25	ns
f_TCLK,FRAM	TCLK/MCLK frequency during JTAG access, including FRAM access (limited by f_SYSTEM with no FRAM wait states)				4	MHz
t_{TCLK,FRAM,Low/High}	TCLK low or high clock pulse duration, including FRAM accesses				100	ns

(1) Tools that access the Spy-Bi-Wire and BSL interfaces must wait for the t_SBW,En time after the first transition of the TEST/SBWTCK pin (low to high), before the second transition of the pin (high to low) during the entry sequence.

(2) f_TCK may be restricted to meet the timing requirements of the module selected.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

サーマルパッド・メカニカル・データ

発注情報

4 Specifications

4.1 Absolute Maximum Ratings(1)

4.2 ESD Ratings

4.3 Recommended Operating Conditions

4.4 Active Mode Supply Current Into VCC Excluding External Current

4.5 Typical Characteristics, Active Mode Supply Currents

4.6 Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current

4.7 Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current

4.8 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current

4.9 Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current

4.10 Typical Characteristics, Low-Power Mode Supply Currents

4.11 Typical Characteristics, Current Consumption per Module(1)

4.12 Thermal Resistance Characteristics

4.13 Timing and Switching Characteristics

4.13.1 Power Supply Sequencing

Table 4-1 Brownout and Device Reset Power Ramp Requirements

Table 4-2 SVS

4.13.2 Reset Timing

Table 4-3 Reset Input

4.13.3 Clock Specifications

Table 4-4 Low-Frequency Crystal Oscillator, LFXT(4)

Table 4-5 High-Frequency Crystal Oscillator, HFXT(5)

Table 4-6 DCO

Table 4-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

Table 4-8 Module Oscillator (MODOSC)

4.13.4 Wake-up Characteristics

Table 4-9 Wake-up Times From Low-Power Modes and Reset

Table 4-10 Typical Wake-up Charge(1)

4.13.4.1 Typical Characteristics, Average LPM Currents vs Wake-up Frequency

4.13.5 Peripherals

4.13.5.1 Digital I/Os

Table 4-11 Digital Inputs

Table 4-12 Digital Outputs

4.13.5.1.1 Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V

Table 4-13 Pin-Oscillator Frequency, Ports Px

4.13.5.1.2 Typical Characteristics, Pin-Oscillator Frequency

4.13.5.2 Timer_A and Timer_B

Table 4-14 Timer_A

Table 4-15 Timer_B

4.13.5.3 eUSCI

Table 4-16 eUSCI (UART Mode) Clock Frequency

Table 4-17 eUSCI (UART Mode)

Table 4-18 eUSCI (SPI Master Mode) Clock Frequency

Table 4-19 eUSCI (SPI Master Mode)

Table 4-20 eUSCI (SPI Slave Mode)

Table 4-21 eUSCI (I2C Mode)

4.13.5.4 LCD Controller

Table 4-22 LCD_C, Recommended Operating Conditions

Table 4-23 LCD_C Electrical Characteristics

4.13.5.5 ADC

Table 4-24 12-Bit ADC, Power Supply and Input Range Conditions

Table 4-25 12-Bit ADC, Timing Parameters

Table 4-26 12-Bit ADC, Linearity Parameters With External Reference(1)

Table 4-27 12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference(2)

Table 4-28 12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference(1)

Table 4-29 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference(1)

Table 4-30 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference(1)

Table 4-31 12-Bit ADC, Dynamic Performance With 32.768-kHz Clock

Table 4-32 12-Bit ADC, Temperature Sensor and Built-In V1/2

Table 4-33 12-Bit ADC, External Reference(1)

4.13.5.6 Reference

Table 4-34 REF, Built-In Reference

4.13.5.7 Comparator

Table 4-35 Comparator_E

4.13.5.8 Scan Interface

Table 4-36 Extended Scan Interface, Port Drive, Port Timing

Table 4-37 Extended Scan Interface, Sample Capacitor/Ri Timing (2)

Table 4-38 Extended Scan Interface, VCC/2 Generator

Table 4-39 Extended Scan Interface, 12-Bit DAC

Table 4-40 Extended Scan Interface, Comparator

Table 4-41 Extended Scan Interface, ESICLK Oscillator and TSM Clock Signals

4.13.5.9 FRAM Controller

Table 4-42 FRAM

4.13.6 Emulation and Debug

Table 4-43 JTAG and Spy-Bi-Wire Interface

4.1 Absolute Maximum Ratings⁽¹⁾

4.4 Active Mode Supply Current Into V_CC Excluding External Current

4.6 Low-Power Mode (LPM0, LPM1) Supply Currents Into V_CC Excluding External Current

4.7 Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into V_CC) Excluding External Current

4.8 Low-Power Mode With LCD Supply Currents (Into V_CC) Excluding External Current

4.9 Low-Power Mode LPMx.5 Supply Currents (Into V_CC) Excluding External Current

4.11 Typical Characteristics, Current Consumption per Module⁽¹⁾

Table 4-4 Low-Frequency Crystal Oscillator, LFXT⁽⁴⁾

Table 4-5 High-Frequency Crystal Oscillator, HFXT⁽⁵⁾

Table 4-10 Typical Wake-up Charge⁽¹⁾

Table 4-21 eUSCI (I²C Mode)

Table 4-26 12-Bit ADC, Linearity Parameters With External Reference⁽¹⁾

Table 4-27 12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference⁽²⁾

Table 4-28 12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference⁽¹⁾

Table 4-29 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference⁽¹⁾

Table 4-30 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference⁽¹⁾

Table 4-32 12-Bit ADC, Temperature Sensor and Built-In V_1/2

Table 4-33 12-Bit ADC, External Reference⁽¹⁾

Table 4-37 Extended Scan Interface, Sample Capacitor/Ri Timing ⁽²⁾

Table 4-38 Extended Scan Interface, V_CC/2 Generator