JAJSCG4A September   2016  – September 2016 ONET1131EC

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Function
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 AC Electrical Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Timing Diagram Definitions
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Equalizer
      2. 7.3.2 CDR
      3. 7.3.3 Modulator Driver
      4. 7.3.4 Modulation Current Generator
      5. 7.3.5 DC Offset Cancellation and Cross Point Control
      6. 7.3.6 Bias Current Generation and APC Loop
      7. 7.3.7 Laser Safety Features and Fault Recovery Procedure
      8. 7.3.8 Analog Block
        1. 7.3.8.1 Analog Reference and Temperature Sensor
        2. 7.3.8.2 Power-On Reset
        3. 7.3.8.3 Analog to Digital Converter
          1. 7.3.8.3.1 Temperature
          2. 7.3.8.3.2 Power Supply Voltage
          3. 7.3.8.3.3 Photodiode Current Monitor
          4. 7.3.8.3.4 Bias Current Monitor
        4. 7.3.8.4 2-Wire Interface and Control Logic
        5. 7.3.8.5 Bus Idle
        6. 7.3.8.6 Start Data Transfer
        7. 7.3.8.7 Stop Data Transfer
        8. 7.3.8.8 Data Transfer
      9. 7.3.9 Acknowledge
    4. 7.4 Device Functional Modes
      1. 7.4.1 Differential Transmitter Output
      2. 7.4.2 Single-Ended Transmitter Output
    5. 7.5 Programming
    6. 7.6 Register Mapping
      1. 7.6.1 R/W Control Registers
        1. 7.6.1.1 Core Level Register 0 (offset = 0100 0001 [reset = 41h]
        2. 7.6.1.2 Core Level Register 1 (offset = 0000 0000) [reset = 0h]
        3. 7.6.1.3 Core Level Register 2 (offset = 0000 0000 ) [reset = 0h]
        4. 7.6.1.4 Core Level Register 3 (offset = 0000 0000) [reset = 0h]
      2. 7.6.2 TX Registers
        1. 7.6.2.1  TX Register 10 (offset = 0000 0000) [reset = 0h]
        2. 7.6.2.2  TX Register 11 (offset = 0000 0000) [reset = 0h]
        3. 7.6.2.3  TX Register 12 (offset = 0000 0000) [reset = 0h]
        4. 7.6.2.4  TX Register 13 (offset = 0h) [reset = 0]
        5. 7.6.2.5  TX Register 14 (offset = 0000 0000) [reset = 0h]
        6. 7.6.2.6  TX Register 15 (offset = 0000 0000) [reset = 0h]
        7. 7.6.2.7  TX Register 16 (offset = 0000 0000) [reset = 0h]
        8. 7.6.2.8  TX Register 17 (offset = 0000 0000) [reset = 0h]
        9. 7.6.2.9  TX Register 18 (offset = 0000 0000) [reset = 0h]
        10. 7.6.2.10 TX Register 19 (offset = 0000 0000) [reset = 0h]
      3. 7.6.3 Reserved Registers
        1. 7.6.3.1 Reserved Registers 20-39
      4. 7.6.4 Read Only Registers
        1. 7.6.4.1 Core Level Register 40 (offset = 0000 0000) [reset = 0h]
        2. 7.6.4.2 Core Level Register 41 (offset = 0000 0000) [reset = 0h]
        3. 7.6.4.3 TX Register 43 (offset = 0000 0000) [reset = 0h]
      5. 7.6.5 Adjustment Registers
        1. 7.6.5.1 Adjustment Registers 44-50
        2. 7.6.5.2 Adjustment Register 51 (offset = 0100 0000) [reset = 40h]
        3. 7.6.5.3 Adjustment Registers 52-55
  8. 8 Application Information and Implementations
    1. 8.1 Application Information
    2. 8.2 Typical Application, Transmitter Differential Mode
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
      4. 8.2.4 Typical Application, Transmitter Single-Ended Mode
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
        3. 8.2.4.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Function

The ONET1131EC is packaged in a small footprint 4 mm x 4 mm 32 pin RoHS compliant QFN package with a lead pitch of 0.4 mm.

RSM Package
32 PIN VQFN
(Top View)
ONET1131EC Pin_Out_SLLSEQ6.gif

Pin Functions

NUMBER NAME Type DESCRIPTION
LOL 1 Digital-out Loss of lock indicator. High level indicates the transmitter CDR is out of lock. Open drain output. Requires an external 4.7 kΩ to 10 kΩ pull-up resistor to VCC for proper operation. This pin is 3.3 V tolerant.
MONB 2 Analog-out Bias current monitor.
GND 3, 6, 19, 22 Supply Circuit ground.
DIN+ 4 Analog-in Non-inverted transmitter data input. On-chip differentially 100 Ω terminated to TXIN–. Must be AC coupled.
DIN– 5 Analog-in Inverted transmitter data input. On-chip differentially 100 Ω terminated to TXIN+. Must be AC coupled.
PD 7 Analog Photodiode input. Pin can source or sink current dependent on register setting.
MONP 8 Analog-out Photodiode current monitor.
LF 9 Analog-in Transmitter loop filter capacitor.
BIAS 10 Analog Sinks or sources the bias current for the laser in both APC and open loop modes.
VCC 11, 14, 27, 30 Supply 2.5 V ± 5% supply.
OUT– 12 CML-out Inverted transmitter data output. Internally terminated in single-ended operation mode.
OUT+ 13 CML-out Non-Inverted transmitter data output.
VDD 15 Supply 2.5 V ± 5% supply for the digital circuitry.
AMP 16 Analog-in Output amplitude control. Output amplitude can be adjusted by applying a voltage of 0 to 2 V to this pin. Leave open when not used.
SDA 17 Digital-in/out 2-wire interface serial data input. Requires an external 4.7-kΩ to10-kΩ pull-up resistor to VCC. This pin is 3.3-V tolerant.
SCK 18 Digital-in 2-wire interface serial clock input. Requires an external 4.7-kΩ to10-kΩ pull-up resistor to VCC. This pin is 3.3-V tolerant.
NC 20, 21, 24, 25, 26, 28, 29 Do not connect
COMP 23 Analog Compensation pin used to control the bandwidth of the APC loop. Connect a 0.01-µF capacitor to ground.
FLT 31 Digital-out Transmitter fault detection flag. High level indicates that a fault has occurred. Open drain output. Requires an external 4.7 kΩ to 10 kΩ pull-up resistor to VCC for proper operation. This pin is 3.3-V tolerant.
DIS 32 Digital-in Disables the bias current when set to high state. Includes a 250-kΩ pull-up resistor to VCC. Requires an external 4.7 kΩ to 10 kΩ pull-up resistor to VCC for proper operation Toggle to reset a fault condition. This is an ORed function with the TXBIASEN bit (bit 2 in register 1). This pin is 3.3-V tolerant.