JAJS010E March   2006  – December 2015 OPA2333 , OPA333


  1. 特長
  2. アプリケーション
  3. 概要
  4. 改訂履歴
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA333
    5. 6.5 Thermal Information: OPA2333
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Voltage
      2. 7.3.2 Input Voltage
      3. 7.3.3 Internal Offset Correction
      4. 7.3.4 Achieving Output Swing to the Op Amp Negative Rail
      5. 7.3.5 DFN Package
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 High-Side Voltage-to-Current (V-I) Converter
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
      2. 8.2.2 Precision, Low-Level Voltage-to-Current (V-I) Converter
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      3. 8.2.3 Composite Amplifier
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
    3. 8.3 System Examples
      1. 8.3.1 Temperature Measurement Application
      2. 8.3.2 Single Operational Amplifier Bridge Amplifier Application
      3. 8.3.3 Low-Side Current Monitor Application
      4. 8.3.4 Other Applications
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General Layout Guidelines
      2. 10.1.2 DFN Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 関連リンク
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報




Layout Guidelines

General Layout Guidelines

Pay attention to good layout practices. Keep traces short and when possible, use a printed-circuit-board (PCB) ground plane with surface-mount components placed as close to the device pins as possible. Place a 0.1-μF capacitor closely across the supply pins. Apply these guidelines throughout the analog circuit to improve performance and provide benefits, such as reducing the electromagnetic interference (EMI) susceptibility.

Operational amplifiers vary in susceptibility to radio frequency interference (RFI). RFI can generally be identified as a variation in offset voltage or DC signal levels with changes in the interfering RF signal. The OPA333 is specifically designed to minimize susceptibility to RFI and demonstrates remarkably low sensitivity compared to previous generation devices. Strong RF fields may still cause varying offset levels.

DFN Layout Guidelines

Solder the exposed leadframe die pad on the DFN package to a thermal pad on the PCB. A mechanical drawing showing an example layout is attached at the end of this data sheet. Refinements to this layout may be necessary based on assembly process requirements. Mechanical drawings located at the end of this data sheet list the physical dimensions for the package and pad. The five holes in the landing pattern are optional, and are intended for use with thermal vias that connect the leadframe die pad to the heatsink area on the PCB.

Soldering the exposed pad significantly improves board-level reliability during temperature cycling, key push, package shear, and similar board-level tests. Even with applications that have low-power dissipation, the exposed pad must be soldered to the PCB to provide structural integrity and long-term reliability.

Layout Example

OPA333 OPA2333 layout_example_bos620.gif Figure 34. Layout Example