JAJSPW7B October   2023  – April 2024 OPA2323 , OPA323 , OPA4323

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information for Single Channel
    5. 6.5 Thermal Information for Dual Channel
    6. 6.6 Thermal Information for Quad Channel
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Operating Voltage
      2. 7.3.2  Rail-to-Rail Input
      3. 7.3.3  Rail-to-Rail Output
      4. 7.3.4  Common-Mode Rejection Ratio (CMRR)
      5. 7.3.5  Capacitive Load and Stability
      6. 7.3.6  Overload Recovery
      7. 7.3.7  EMI Rejection
      8. 7.3.8  ESD and Electrical Overstress
      9. 7.3.9  Input ESD Protection
      10. 7.3.10 Shutdown Function
      11. 7.3.11 Packages with an Exposed Thermal Pad
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 OPAx323 in Low-Side, Current Sensing Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4.     Trademarks
    5. 9.4 静電気放電に関する注意事項
    6. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DYY|14
  • PW|14
サーマルパッド・メカニカル・データ
発注情報

7.3.2 Rail-to-Rail Input

The input common-mode voltage range of the OPAx323 series extends beyond the supply rails with a common-mode rejection ratio (CMRR) of 100dB minimum at 5.5V as specified in Electrical Characteristics. The device is designed to have a good performance of 85dB minimum CMRR even when operating at an ultra-low supply voltage of 1.8V. This is made possible by using a zero-cross input stage architecture for the amplifier input pair.

Most commercial amplifiers employ a complementary input stage architecture which often limits the rail-to-rail CMRR to less than 65dB. This is because the offset performance across the rail-to-rail input common-mode range is not linear. One of the input pairs, usually, the P-channel pair with better offset, noise performance is designed to cover the majority of the common-mode range with the N-channel pair slated to slowly take over at a certain threshold voltage from the positive rail. The creates a big jump in the offset voltage across common mode when transitioning across the input pairs as shown in TLV900x Offset Voltage vs Common-Mode. This offset jump not only affects CMRR but also limits linearity / THD for rail-to-rail input signals.

The OPAx323 achieves linear offset performance over the entire rail-to-rail input range by extending the common-mode-range of a single P-channel input pair using an internal charge pump as shown in the Functional Block Diagram. This eliminates the need for the N-channel input pair and the resulting offset jump caused by input pair transitions.

The OPAx323 exhibits near to zero shift in offset voltage across the entire common-mode voltage as shown in Figure 7-72. This is crucial to achieving high linearity in ADC driver and audio driver applications.

GUID-20240213-SS0I-S5JH-GZHT-R4BG2M5KZ6L0-low.gif
V+ = 2.75V, V– = –2.75V No. of devices = 45
(V–) – 0.25V < VCM < (V+) + 0.15V
Figure 7-1 OPAx323 Offset Voltage vs Common-Mode
GUID-19EC3167-EB20-4225-A64C-F253BAD9DA0F-low.gif
V+ = 2.75V, V– = –2.75V
Figure 7-2 TLV900x Offset Voltage vs Common-Mode