JAJSKT0 December   2020 PCM6020-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: I2C Interface
    7. 7.7  Switching Characteristics: I2C Interface
    8. 7.8  Timing Requirements: SPI Interface
    9. 7.9  Switching Characteristics: SPI Interface
    10. 7.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 7.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 7.12 Timing Diagrams
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Serial Interfaces
        1. 8.3.1.1 Control Serial Interfaces
        2. 8.3.1.2 Audio Serial Interfaces
          1. 8.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 8.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 8.3.1.2.3 Left-Justified (LJ) Interface
        3. 8.3.1.3 Using Multiple Devices With Shared Buses
      2. 8.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 8.3.3 Input Channel Configuration
      4. 8.3.4 Reference Voltage
      5. 8.3.5 Microphone Bias
      6. 8.3.6 Input DC Fault Diagnostics
        1. 8.3.6.1 Fault Conditions
          1. 8.3.6.1.1 Input Pin Short to Ground
          2. 8.3.6.1.2 Input Pin Short to MICBIAS
          3. 8.3.6.1.3 Open Inputs
          4. 8.3.6.1.4 Short Between INxP and INxM
          5. 8.3.6.1.5 Input Pin Overvoltage
          6. 8.3.6.1.6 Input Pin Short to VBAT_IN
        2. 8.3.6.2 Fault Reporting
          1. 8.3.6.2.1 Overcurrent and Overtemperature Protection
      7. 8.3.7 Signal-Chain Processing
        1. 8.3.7.1 Programmable Channel Gain and Digital Volume Control
        2. 8.3.7.2 Programmable Channel Gain Calibration
        3. 8.3.7.3 Programmable Channel Phase Calibration
        4. 8.3.7.4 Programmable Digital High-Pass Filter
        5. 8.3.7.5 Programmable Digital Biquad Filters
        6. 8.3.7.6 Programmable Channel Summer and Digital Mixer
        7. 8.3.7.7 Configurable Digital Decimation Filters
          1. 8.3.7.7.1 Linear Phase Filters
            1. 8.3.7.7.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 8.3.7.7.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 8.3.7.7.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 8.3.7.7.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 8.3.7.7.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 8.3.7.7.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 8.3.7.7.1.7 Sampling Rate: 192 kHz or 176.4 kHz
            8. 8.3.7.7.1.8 Sampling Rate: 384 kHz or 352.8 kHz
            9. 8.3.7.7.1.9 Sampling Rate: 768 kHz or 705.6 kHz
          2. 8.3.7.7.2 Low-Latency Filters
            1. 8.3.7.7.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.7.7.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.7.7.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.7.7.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.7.7.2.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 8.3.7.7.2.6 Sampling Rate: 192 kHz or 176.4 kHz
          3. 8.3.7.7.3 Ultra-Low-Latency Filters
            1. 8.3.7.7.3.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.7.7.3.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.7.7.3.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.7.7.3.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.7.7.3.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 8.3.7.7.3.6 Sampling Rate: 192 kHz or 176.4 kHz
            7. 8.3.7.7.3.7 Sampling Rate: 384 kHz or 352.8 kHz
      8. 8.3.8 Automatic Gain Controller (AGC)
      9. 8.3.9 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 8.4 Device Functional Modes
      1. 8.4.1 Hardware Shutdown
      2. 8.4.2 Sleep Mode or Software Shutdown
      3. 8.4.3 Active Mode
      4. 8.4.4 Software Reset
    5. 8.5 Programming
      1. 8.5.1 Control Serial Interfaces
        1. 8.5.1.1 I2C Control Interface
          1. 8.5.1.1.1 General I2C Operation
          2. 8.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 8.5.1.1.2.1 I2C Single-Byte Write
            2. 8.5.1.1.2.2 I2C Multiple-Byte Write
            3. 8.5.1.1.2.3 I2C Single-Byte Read
            4. 8.5.1.1.2.4 I2C Multiple-Byte Read
        2. 8.5.1.2 SPI Control Interface
    6. 8.6 Register Maps
      1. 8.6.1 Device Configuration Registers
        1. 8.6.1.1 Registers Access Type
        2. 8.6.1.2 Page 0 Registers
        3. 8.6.1.3 Page 1 Registers
      2. 8.6.2 Programmable Coefficient Registers
        1. 8.6.2.1 Programmable Coefficient Registers: Page 2
        2. 8.6.2.2 Programmable Coefficient Registers: Page 3
        3. 8.6.2.3 Programmable Coefficient Registers: Page 4
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 2-Channel Analog Microphone Recording Using the PCM6020-Q1
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Example Device Register Configuration Script for EVM Setup
        3. 9.2.1.3 Application Curves
    3. 9.3 What To Do and What Not To Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
      1.      Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.6.2.2 Programmable Coefficient Registers: Page 3

This register page (shown in Table 8-143) consists of the programmable coefficients for the biquad 9 and biquad 10 filters. To optimize the coefficients register transaction time for page 2, page 3, and page 4, the device also supports (by default) auto-incremented pages for the I2C and SPI burst writes and reads. After a transaction of register address 0x7F, the device auto increments to the next page at register 0x08 to transact the next coefficient value. These programmable coefficients are 32-bit, two’s complement numbers. For a successful coefficient register transaction, the host device must write and read all four bytes starting with the most significant byte (BYT1) for a target coefficient register transaction. When using SPI for a coefficient register read transaction, the device transmits the first byte as a dummy read byte; therefore, the host must read five bytes, including the first dummy read byte and the last four bytes corresponding to the coefficient register value starting with the most significant byte (BYT1).

Table 8-143 Page 3 Programmable Coefficient Registers
ADDRESS ACRONYM RESET VALUE REGISTER DESCRIPTION
0x00 PAGE[7:0] 0x00 Section 6.1.2.1
0x30 BQ9_N0_BYT1[7:0] 0x7F Programmable biquad 9, N0 coefficient byte[31:24]
0x31 BQ9_N0_BYT2[7:0] 0xFF Programmable biquad 9, N0 coefficient byte[23:16]
0x32 BQ9_N0_BYT3[7:0] 0xFF Programmable biquad 9, N0 coefficient byte[15:8]
0x33 BQ9_N0_BYT4[7:0] 0xFF Programmable biquad 9, N0 coefficient byte[7:0]
0x34 BQ9_N1_BYT1[7:0] 0x00 Programmable biquad 9, N1 coefficient byte[31:24]
0x35 BQ9_N1_BYT2[7:0] 0x00 Programmable biquad 9, N1 coefficient byte[23:16]
0x36 BQ9_N1_BYT3[7:0] 0x00 Programmable biquad 9, N1 coefficient byte[15:8]
0x37 BQ9_N1_BYT4[7:0] 0x00 Programmable biquad 9, N1 coefficient byte[7:0]
0x38 BQ9_N2_BYT1[7:0] 0x00 Programmable biquad 9, N2 coefficient byte[31:24]
0x39 BQ9_N2_BYT2[7:0] 0x00 Programmable biquad 9, N2 coefficient byte[23:16]
0x3A BQ9_N2_BYT3[7:0] 0x00 Programmable biquad 9, N2 coefficient byte[15:8]
0x3B BQ9_N2_BYT4[7:0] 0x00 Programmable biquad 9, N2 coefficient byte[7:0]
0x3C BQ9_D1_BYT1[7:0] 0x00 Programmable biquad 9, D1 coefficient byte[31:24]
0x3D BQ9_D1_BYT2[7:0] 0x00 Programmable biquad 9, D1 coefficient byte[23:16]
0x3E BQ9_D1_BYT3[7:0] 0x00 Programmable biquad 9, D1 coefficient byte[15:8]
0x3F BQ9_D1_BYT4[7:0] 0x00 Programmable biquad 9, D1 coefficient byte[7:0]
0x40 BQ9_D2_BYT1[7:0] 0x00 Programmable biquad 9, D2 coefficient byte[31:24]
0x41 BQ9_D2_BYT2[7:0] 0x00 Programmable biquad 9, D2 coefficient byte[23:16]
0x42 BQ9_D2_BYT3[7:0] 0x00 Programmable biquad 9, D2 coefficient byte[15:8]
0x43 BQ9_D2_BYT4[7:0] 0x00 Programmable biquad 9, D2 coefficient byte[7:0]
0x44 BQ10_N0_BYT1[7:0] 0x7F Programmable biquad 10, N0 coefficient byte[31:24]
0x45 BQ10_N0_BYT2[7:0] 0xFF Programmable biquad 10, N0 coefficient byte[23:16]
0x46 BQ10_N0_BYT3[7:0] 0xFF Programmable biquad 10, N0 coefficient byte[15:8]
0x47 BQ10_N0_BYT4[7:0] 0xFF Programmable biquad 10, N0 coefficient byte[7:0]
0x48 BQ10_N1_BYT1[7:0] 0x00 Programmable biquad 10, N1 coefficient byte[31:24]
0x49 BQ10_N1_BYT2[7:0] 0x00 Programmable biquad 10, N1 coefficient byte[23:16]
0x4A BQ10_N1_BYT3[7:0] 0x00 Programmable biquad 10, N1 coefficient byte[15:8]
0x4B BQ10_N1_BYT4[7:0] 0x00 Programmable biquad 10, N1 coefficient byte[7:0]
0x4C BQ10_N2_BYT1[7:0] 0x00 Programmable biquad 10, N2 coefficient byte[31:24]
0x4D BQ10_N2_BYT2[7:0] 0x00 Programmable biquad 10, N2 coefficient byte[23:16]
0x4E BQ10_N2_BYT3[7:0] 0x00 Programmable biquad 10, N2 coefficient byte[15:8]
0x4F BQ10_N2_BYT4[7:0] 0x00 Programmable biquad 10, N2 coefficient byte[7:0]
0x50 BQ10_D1_BYT1[7:0] 0x00 Programmable biquad 10, D1 coefficient byte[31:24]
0x51 BQ10_D1_BYT2[7:0] 0x00 Programmable biquad 10, D1 coefficient byte[23:16]
0x52 BQ10_D1_BYT3[7:0] 0x00 Programmable biquad 10, D1 coefficient byte[15:8]
0x53 BQ10_D1_BYT4[7:0] 0x00 Programmable biquad 10, D1 coefficient byte[7:0]
0x54 BQ10_D2_BYT1[7:0] 0x00 Programmable biquad 10, D2 coefficient byte[31:24]
0x55 BQ10_D2_BYT2[7:0] 0x00 Programmable biquad 10, D2 coefficient byte[23:16]
0x56 BQ10_D2_BYT3[7:0] 0x00 Programmable biquad 10, D2 coefficient byte[15:8]
0x57 BQ10_D2_BYT4[7:0] 0x00 Programmable biquad 10, D2 coefficient byte[7:0]