JAJSKT9A December   2020  – June 2021 PCMD3140

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: TDM, I2S or LJ Interface
    9. 6.9  Switching Characteristics: TDM, I2S or LJ Interface
    10. 6.10 Timing Requirements: PDM Digital Microphone Interface
    11. 6.11 Switching Characteristics: PDM Digial Microphone Interface
    12. 6.12 Timing Diagrams
    13. 6.13 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Interfaces
        1. 7.3.1.1 Control Serial Interfaces
        2. 7.3.1.2 Audio Serial Interfaces
          1. 7.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 7.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 7.3.1.2.3 Left-Justified (LJ) Interface
        3. 7.3.1.3 Using Multiple Devices With Shared Buses
      2. 7.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 7.3.3 Reference Voltage
      4. 7.3.4 Microphone Bias
      5. 7.3.5 Digital PDM Microphone Record Channel
      6. 7.3.6 Signal-Chain Processing
        1. 7.3.6.1 Programmable Digital Volume Control
        2. 7.3.6.2 Programmable Channel Gain Calibration
        3. 7.3.6.3 Programmable Channel Phase Calibration
        4. 7.3.6.4 Programmable Digital High-Pass Filter
        5. 7.3.6.5 Programmable Digital Biquad Filters
        6. 7.3.6.6 Programmable Channel Summer and Digital Mixer
        7. 7.3.6.7 Configurable Digital Decimation Filters
          1. 7.3.6.7.1 Linear Phase Filters
            1. 7.3.6.7.1.1 Sampling Rate: 7.35 kHz to 8 kHz
            2. 7.3.6.7.1.2 Sampling Rate: 14.7 kHz to 16 kHz
            3. 7.3.6.7.1.3 Sampling Rate: 22.05 kHz to 24 kHz
            4. 7.3.6.7.1.4 Sampling Rate: 29.4 kHz to 32 kHz
            5. 7.3.6.7.1.5 Sampling Rate: 44.1 kHz to 48 kHz
            6. 7.3.6.7.1.6 Sampling Rate: 88.2 kHz to 96 kHz
            7. 7.3.6.7.1.7 Sampling Rate: 176.4 kHz to 192 kHz
            8. 7.3.6.7.1.8 Sampling Rate: 352.8 kHz to 384 kHz
            9. 7.3.6.7.1.9 Sampling Rate: 705.6 kHz to 768 kHz
          2. 7.3.6.7.2 Low-Latency Filters
            1. 7.3.6.7.2.1 Sampling Rate: 14.7 kHz to 16 kHz
            2. 7.3.6.7.2.2 Sampling Rate: 22.05 kHz to 24 kHz
            3. 7.3.6.7.2.3 Sampling Rate: 29.4 kHz to 32 kHz
            4. 7.3.6.7.2.4 Sampling Rate: 44.1 kHz to 48 kHz
            5. 7.3.6.7.2.5 Sampling Rate: 88.2 kHz to 96 kHz
            6. 7.3.6.7.2.6 Sampling Rate: 176.4 kHz to 192 kHz
          3. 7.3.6.7.3 Ultra-Low-Latency Filters
            1. 7.3.6.7.3.1 Sampling Rate: 14.7 kHz to 16 kHz
            2. 7.3.6.7.3.2 Sampling Rate: 22.05 kHz to 24 kHz
            3. 7.3.6.7.3.3 Sampling Rate: 29.4 kHz to 32 kHz
            4. 7.3.6.7.3.4 Sampling Rate: 44.1 kHz to 48 kHz
            5. 7.3.6.7.3.5 Sampling Rate: 88.2 kHz to 96 kHz
            6. 7.3.6.7.3.6 Sampling Rate: 176.4 kHz to 192 kHz
            7. 7.3.6.7.3.7 Sampling Rate: 352.8 kHz to 384 kHz
      7. 7.3.7 Voice Activity Detection (VAD)
      8. 7.3.8 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode or Software Shutdown
      2. 7.4.2 Active Mode
      3. 7.4.3 Software Reset
    5. 7.5 Programming
      1. 7.5.1 Control Serial Interfaces
        1. 7.5.1.1 I2C Control Interface
          1. 7.5.1.1.1 General I2C Operation
          2. 7.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 7.5.1.1.2.1 I2C Single-Byte Write
            2. 7.5.1.1.2.2 I2C Multiple-Byte Write
            3. 7.5.1.1.2.3 I2C Single-Byte Read
            4. 7.5.1.1.2.4 I2C Multiple-Byte Read
    6. 7.6 Register Maps
      1. 7.6.1 Page 0 Registers
      2. 7.6.2 Page 1 Registers
      3. 7.6.3 Programmable Coefficient Registers
        1. 7.6.3.1 Programmable Coefficient Registers: Page 2
        2. 7.6.3.2 Programmable Coefficient Registers: Page 3
        3. 7.6.3.3 Programmable Coefficient Registers: Page 4
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Four-Channel Digital PDM Microphone Recording
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Example Device Register Configuration Script for EVM Setup
        3. 8.2.1.3 Application Curves
    3. 8.3 What to Do and What Not to Do
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.3 Reference Voltage

The PCMD3140 achieves low-noise performance by internally generating a low-noise reference voltage. This reference voltage is generated using a band-gap circuit with high PSRR performance and must be filtered externally using a 1-µF capacitor connected from the VREF pin to analog ground (AVSS).

The value of this reference voltage can be configured using the P0_R59_D[1:0] register bits and must be set to an appropriate value based on the AVDD supply voltage available in the system. The default VREF value is set to 2.75 V, which require minimum AVDD voltage for this mode is 3 V. Table 7-8 lists the various VREF settings supported along with required AVDD range for that configuration.

Table 7-8 VREF Programmable Settings
P0_R59_D[1:0] : VREF_SEL[1:0] VREF OUTPUT VOLTAGE AVDD RANGE REQUIREMENT
00 (default) 2.75 V 3 V to 3.6 V
01 2.5 V 2.8 V to 3.6 V
10 1.375 V 1.7 V to 1.9 V
11 Reserved Reserved

To achieve low-power consumption, this audio reference block is powered down as described in the Section 7.4.1 section. When exiting sleep mode, the audio reference block is powered up using the internal fast-charge scheme and the VREF pin settles to its steady-state voltage after the settling time (a function of the decoupling capacitor on the VREF pin). This time is approximately equal to 3.5 ms when using a 1-μF decoupling capacitor. If a higher-value decoupling capacitor is used on the VREF pin, the fast-charge setting must be reconfigured using the VREF_QCHG (P0_R2_D[4:3]) register bits, which support options of 3.5 ms (default), 10 ms, 50 ms, or 100 ms.