JAJSSH9A May   2023  – January 2024 PCMD3180-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: I2C Interface
    7. 5.7  Switching Characteristics: I2C Interface
    8. 5.8  Timing Requirements: SPI Interface
    9. 5.9  Switching Characteristics: SPI Interface
    10. 5.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 5.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 5.12 Timing Requirements: PDM Digital Microphone Interface
    13. 5.13 Switching Characteristics: PDM Digial Microphone Interface
    14. 5.14 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
        3. 6.3.1.3 Using Multiple Devices With Shared Buses
      2. 6.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 6.3.3 Reference Voltage
      4. 6.3.4 Microphone Bias
      5. 6.3.5 Digital PDM Microphone Record Channel
      6. 6.3.6 Signal-Chain Processing
        1. 6.3.6.1 Programmable Digital Volume Control
        2. 6.3.6.2 Programmable Channel Gain Calibration
        3. 6.3.6.3 Programmable Channel Phase Calibration
        4. 6.3.6.4 Programmable Digital High-Pass Filter
        5. 6.3.6.5 Programmable Digital Biquad Filters
        6. 6.3.6.6 Programmable Channel Summer and Digital Mixer
        7. 6.3.6.7 Configurable Digital Decimation Filters
          1. 6.3.6.7.1 Linear Phase Filters
            1. 6.3.6.7.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 6.3.6.7.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 6.3.6.7.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 6.3.6.7.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 6.3.6.7.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 6.3.6.7.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 6.3.6.7.1.7 Sampling Rate: 192 kHz or 176.4 kHz
            8. 6.3.6.7.1.8 Sampling Rate: 384 kHz or 352.8 kHz
            9. 6.3.6.7.1.9 Sampling Rate 768 kHz or 705.6 kHz
          2. 6.3.6.7.2 Low-Latency Filters
            1. 6.3.6.7.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 6.3.6.7.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 6.3.6.7.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 6.3.6.7.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 6.3.6.7.2.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 6.3.6.7.2.6 Sampling Rate 192 kHz or 176.4 kHz
          3. 6.3.6.7.3 Ultra-Low-Latency Filters
            1. 6.3.6.7.3.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 6.3.6.7.3.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 6.3.6.7.3.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 6.3.6.7.3.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 6.3.6.7.3.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 6.3.6.7.3.6 Sampling Rate 192 kHz or 176.4 kHz
            7. 6.3.6.7.3.7 Sampling Rate 384 kHz or 352.8 kHz
      7. 6.3.7 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 6.4 Device Functional Modes
      1. 6.4.1 Hardware Shutdown
      2. 6.4.2 Sleep Mode or Software Shutdown
      3. 6.4.3 Active Mode
      4. 6.4.4 Software Reset
    5. 6.5 Programming
      1. 6.5.1 Control Serial Interfaces
        1. 6.5.1.1 I2C Control Interface
          1. 6.5.1.1.1 General I2C Operation
          2. 6.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 6.5.1.1.2.1 I2C Single-Byte Write
            2. 6.5.1.1.2.2 I2C Multiple-Byte Write
            3. 6.5.1.1.2.3 I2C Single-Byte Read
            4. 6.5.1.1.2.4 I2C Multiple-Byte Read
        2. 6.5.1.2 SPI Control Interface
  8. 7 Register Maps
    1. 7.1 Device Configuration Registers
      1. 7.1.1 Register Summary Table Page=0x00
      2. 7.1.2 88
      3. 7.1.3 Register Descriptions
        1. 7.1.3.1  PAGE_CFG Register (page = 0x00, address = 0x00) [reset = 0h]
        2. 7.1.3.2  SW_RESET Register (page = 0x00, address = 0x01) [reset = 0h]
        3. 7.1.3.3  SLEEP_CFG Register (page = 0x00, address = 0x02) [reset = 0h]
        4. 7.1.3.4  SHDN_CFG Register (page = 0x00, address = 0x05) [reset = 5h]
        5. 7.1.3.5  ASI_CFG0 Register (page = 0x00, address = 0x07) [reset = 30h]
        6. 7.1.3.6  ASI_CFG1 Register (page = 0x00, address = 0x08) [reset = 0h]
        7. 7.1.3.7  ASI_CFG2 Register (page = 0x00, address = 0x09) [reset = 0h]
        8. 7.1.3.8  ASI_CH1 Register (page = 0x00, address = 0x0B) [reset = 0h]
        9. 7.1.3.9  ASI_CH2 Register (page = 0x00, address = 0x0C) [reset = 1h]
        10. 7.1.3.10 ASI_CH3 Register (page = 0x00, address = 0x0D) [reset = 2h]
        11. 7.1.3.11 ASI_CH4 Register (page = 0x00, address = 0x0E) [reset = 3h]
        12. 7.1.3.12 ASI_CH5 Register (page = 0x00, address = 0x0F) [reset = 4h]
        13. 7.1.3.13 ASI_CH6 Register (page = 0x00, address = 0x10) [reset = 5h]
        14. 7.1.3.14 ASI_CH7 Register (page = 0x00, address = 0x11) [reset = 6h]
        15. 7.1.3.15 ASI_CH8 Register (page = 0x00, address = 0x12) [reset = 7h]
        16. 7.1.3.16 MST_CFG0 Register (page = 0x00, address = 0x13) [reset = 2h]
        17. 7.1.3.17 MST_CFG1 Register (page = 0x00, address = 0x14) [reset = 48h]
        18. 7.1.3.18 ASI_STS Register (page = 0x00, address = 0x15) [reset = FFh]
        19. 7.1.3.19 CLK_SRC Register (page = 0x00, address = 0x16) [reset = 10h]
        20. 7.1.3.20 PDMCLK_CFG Register (page = 0x00, address = 0x1F) [reset = 40h]
        21. 7.1.3.21 PDMIN_CFG Register (page = 0x00, address = 0x20) [reset = 0h]
        22. 7.1.3.22 GPIO_CFG0 Register (page = 0x00, address = 0x21) [reset = 22h]
        23. 7.1.3.23 GPO_CFG0 Register (page = 0x00, address = 0x22) [reset = 0h]
        24. 7.1.3.24 GPO_CFG1 Register (page = 0x00, address = 0x23) [reset = 0h]
        25. 7.1.3.25 GPO_CFG2 Register (page = 0x00, address = 0x24) [reset = 0h]
        26. 7.1.3.26 PO_CFG3 Register (page = 0x00, address = 0x25) [reset = 0h]
        27. 7.1.3.27 GPO_VAL Register (page = 0x00, address = 0x29) [reset = 0h]
        28. 7.1.3.28 GPIO_MON Register (page = 0x00, address = 0x2A) [reset = 0h]
        29. 7.1.3.29 GPI_CFG0 Register (page = 0x00, address = 0x2B) [reset = 0h]
        30. 7.1.3.30 GPI_CFG1 Register (page = 0x00, address = 0x2C) [reset = 0h]
        31. 7.1.3.31 GPI_MON Register (page = 0x00, address = 0x2F) [reset = 0h]
        32. 7.1.3.32 INT_CFG Register (page = 0x00, address = 0x32) [reset = 0h]
        33. 7.1.3.33 INT_MASK0 Register (page = 0x00, address = 0x33) [reset = FFh]
        34. 7.1.3.34 INT_LTCH0 Register (page = 0x00, address = 0x36) [reset = 0h]
        35. 7.1.3.35 BIAS_CFG Register (page = 0x00, address = 0x3B) [reset = 0h]
        36. 7.1.3.36 CH1_CFG0 Register (page = 0x00, address = 0x3C) [reset = 0h]
        37. 7.1.3.37 CH1_CFG2 Register (page = 0x00, address = 0x3E) [reset = C9h]
        38. 7.1.3.38 CH1_CFG3 Register (page = 0x00, address = 0x3F) [reset = 80h]
        39. 7.1.3.39 CH1_CFG4 Register (page = 0x00, address = 0x40) [reset = 0h]
        40. 7.1.3.40 CH2_CFG0 Register (page = 0x00, address = 0x41) [reset = 0h]
        41. 7.1.3.41 CH2_CFG2 Register (page = 0x00, address = 0x43) [reset = C9h]
        42. 7.1.3.42 CH2_CFG3 Register (page = 0x00, address = 0x44) [reset = 80h]
        43. 7.1.3.43 CH2_CFG4 Register (page = 0x00, address = 0x45) [reset = 0h]
        44. 7.1.3.44 CH3_CFG0 Register (page = 0x00, address = 0x46) [reset = 0h]
        45. 7.1.3.45 CH3_CFG2 Register (page = 0x00, address = 0x48) [reset = C9h]
        46. 7.1.3.46 CH3_CFG3 Register (page = 0x00, address = 0x49) [reset = 80h]
        47. 7.1.3.47 CH3_CFG4 Register (page = 0x00, address = 0x4A) [reset = 0h]
        48. 7.1.3.48 CH4_CFG0 Register (page = 0x00, address = 0x4B) [reset = 0h]
        49. 7.1.3.49 CH4_CFG2 Register (page = 0x00, address = 0x4D) [reset = C9h]
        50. 7.1.3.50 CH4_CFG3 Register (page = 0x00, address = 0x4E) [reset = 80h]
        51. 7.1.3.51 CH4_CFG4 Register (page = 0x00, address = 0x4F) [reset = 0h]
        52. 7.1.3.52 CH5_CFG0 Register (page = 0x00, address = 0x50) [reset = 0h]
        53. 7.1.3.53 CH5_CFG2 Register (page = 0x00, address = 0x52) [reset = C9h]
        54. 7.1.3.54 CH5_CFG3 Register (page = 0x00, address = 0x53) [reset = 80h]
        55. 7.1.3.55 CH5_CFG4 Register (page = 0x00, address = 0x54) [reset = 0h]
        56. 7.1.3.56 CH6_CFG0 Register (page = 0x00, address = 0x55) [reset = 0h]
        57. 7.1.3.57 CH6_CFG2 Register (page = 0x00, address = 0x57) [reset = C9h]
        58. 7.1.3.58 CH6_CFG3 Register (page = 0x00, address = 0x58) [reset = 80h]
        59. 7.1.3.59 CH6_CFG4 Register (page = 0x00, address = 0x59) [reset = 0h]
        60. 7.1.3.60 CH7_CFG0 Register (page = 0x00, address = 0x5A) [reset = 0h]
        61. 7.1.3.61 CH7_CFG2 Register (page = 0x00, address = 0x5C) [reset = C9h]
        62. 7.1.3.62 CH7_CFG3 Register (page = 0x00, address = 0x5D) [reset = 80h]
        63. 7.1.3.63 CH7_CFG4 Register (page = 0x00, address = 0x5E) [reset = 0h]
        64. 7.1.3.64 CH8_CFG0 Register (page = 0x00, address = 0x5F) [reset = 0h]
        65. 7.1.3.65 CH8_CFG2 Register (page = 0x00, address = 0x61) [reset = C9h]
        66. 7.1.3.66 CH8_CFG3 Register (page = 0x00, address = 0x62) [reset = 80h]
        67. 7.1.3.67 CH8_CFG4 Register (page = 0x00, address = 0x63) [reset = 0h]
        68. 7.1.3.68 DSP_CFG0 Register (page = 0x00, address = 0x6B) [reset = 1h]
        69. 7.1.3.69 DSP_CFG1 Register (page = 0x00, address = 0x6C) [reset = 40h]
        70. 7.1.3.70 IN_CH_EN Register (page = 0x00, address = 0x73) [reset = F0h]
        71. 7.1.3.71 ASI_OUT_CH_EN Register (page = 0x00, address = 0x74) [reset = 0h]
        72. 7.1.3.72 PWR_CFG Register (page = 0x00, address = 0x75) [reset = 0h]
        73. 7.1.3.73 DEV_STS0 Register (page = 0x00, address = 0x76) [reset = 0h]
        74. 7.1.3.74 DEV_STS1 Register (page = 0x00, address = 0x77) [reset = 80h]
        75. 7.1.3.75 I2C_CKSUM Register (page = 0x00, address = 0x7E) [reset = 0h]
    2. 7.2 Programmable Coefficient Registers
      1. 7.2.1 Programmable Coefficient Registers: Page = 0x02
      2. 7.2.2 Programmable Coefficient Registers: Page = 0x03
      3. 7.2.3 Programmable Coefficient Registers: Page = 0x04
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Eight-Channel Digital PDM Microphone Recording
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Example Device Register Configuration Script for EVM Setup
        3. 8.2.1.3 Application Curves
    3. 8.3 What to Do and What Not to Do
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.1.1 Register Summary Table Page=0x00

ADDRESSREGISTERDESCRIPTIONSECTION
0x00PAGE_CFGDevice page registerPAGE_CFG Register (P0_R0)
0x01SW_RESETSoftware reset registerSW_RESET Register (P0_R1)
0x02SLEEP_CFGSleep mode registerSLEEP_CFG Register (P0_R2)
0x05SHDN_CFGShutdown configuration registerSHDN_CFG Register (P0_R5)
0x07ASI_CFG0ASI configuration register 0ASI_CFG0 Register (P0_R7)
0x08ASI_CFG1ASI configuration register 1ASI_CFG1 Register (P0_R8)
0x09ASI_CFG2ASI configuration register 2ASI_CFG2 Register (P0_R9)
0x0BASI_CH1Channel 1 ASI slot configuration registerASI_CH1 Register (P0_R11)
0x0CASI_CH2Channel 2 ASI slot configuration registerASI_CH2 Register (P0_R12)
0x0DASI_CH3Channel 3 ASI slot configuration registerASI_CH3 Register (P0_R13)
0x0EASI_CH4Channel 4 ASI slot configuration registerASI_CH4 Register (P0_R14)
0x0FASI_CH5Channel 5 ASI slot configuration registerASI_CH5 Register (P0_R15)
0x10ASI_CH6Channel 6 ASI slot configuration registerASI_CH6 Register (P0_R16)
0x11ASI_CH7Channel 7 ASI slot configuration registerASI_CH7 Register (P0_R17)
0x12ASI_CH8Channel 8 ASI slot configuration registerASI_CH8 Register (P0_R18)
0x13MST_CFG0ASI controller mode configuration register 0MST_CFG0 Register (P0_R19)
0x14MST_CFG1ASI controller mode configuration register 1MST_CFG1 Register (P0_R20)
0x15ASI_STSASI bus clock monitor status registerASI_STS Register (P0_R21)
0x16CLK_SRCClock source configuration register 0CLK_SRC Register (P0_R22)
0x1FPDMCLK_CFGPDM clock generation configuration registerPDMCLK_CFG Register (P0_R31)
0x20PDMIN_CFGPDM DINx sampling edge registerPDMIN_CFG Register (P0_R32)
0x21GPIO_CFG0GPIO configuration register 0GPIO_CFG0 Register (P0_R33)
0x22GPO_CFG0GPO configuration register 0GPO_CFG0 Register (P0_R34)
0x23GPO_CFG1GPO configuration register 1GPO_CFG1 Register (P0_R35)
0x24GPO_CFG2GPO configuration register 2GPO_CFG2 Register (P0_R36)
0x25GPO_CFG3GPO configuration register 3GPO_CFG3 Register (P0_R37)
0x29GPO_VALGPIO, GPO output value registerGPO_VAL Register (P0_R41)
0x2AGPIO_MONGPIO monitor value registerGPIO_MON Register (P0_R42)
0x2BGPI_CFG0GPI configuration register 0GPI_CFG0 Register (P0_R43)
0x2CGPI_CFG1GPI configuration register 1GPI_CFG1 Register (P0_R44)
0x2FGPI_MONGPI monitor value registerGPI_MON Register (P0_R47)
0x32INT_CFGInterrupt configuration registerINT_CFG Register (P0_R50)
0x33INT_MASK0Interrupt mask register 0INT_MASK0 Register (P0_R51)
0x36INT_LTCH0Latched interrupt readback register 0INT_LTCH0 Register (P0_R54)
0x3BBIAS_CFGMICBIAS and VREF configuration registerBIAS_CFG Register (P0_R59)
0x3CCH1_CFG0Channel 1 configuration register 0CH1_CFG0 Register (P0_R60)
0x3ECH1_CFG2Channel 1 configuration register 2CH1_CFG2 Register (P0_R62)
0x3FCH1_CFG3Channel 1 configuration register 3CH1_CFG3 Register (P0_R63)
0x40CH1_CFG4Channel 1 configuration register 4CH1_CFG4 Register (P0_R64)
0x41CH2_CFG0Channel 2 configuration register 0CH2_CFG0 Register (P0_R65)
0x43CH2_CFG2Channel 2 configuration register 2CH2_CFG2 Register (P0_R67)
0x44CH2_CFG3Channel 2 configuration register 3CH2_CFG3 Register (P0_R68)
0x45CH2_CFG4Channel 2 configuration register 4CH2_CFG4 Register (P0_R69)
0x46CH3_CFG0Channel 3 configuration register 0CH3_CFG0 Register (P0_R70)
0x48CH3_CFG2Channel 3 configuration register 2CH3_CFG2 Register (P0_R72)
0x49CH3_CFG3Channel 3 configuration register 3CH3_CFG3 Register (P0_R73)
0x4ACH3_CFG4Channel 3 configuration register 4CH3_CFG4 Register (P0_R74)
0x4BCH4_CFG0Channel 4 configuration register 0CH4_CFG0 Register (P0_R75)
0x4DCH4_CFG2Channel 4 configuration register 2CH4_CFG2 Register (P0_R77)
0x4ECH4_CFG3Channel 4 configuration register 3CH4_CFG3 Register (P0_R78)
0x4FCH4_CFG4Channel 4 configuration register 4CH4_CFG4 Register (P0_R79)
0x50CH5_CFG0Channel 5 configuration register 0CH5_CFG0 Register (P0_R80)
0x52CH5_CFG2Channel 5 configuration register 2CH5_CFG2 Register (P0_R82)
0x53CH5_CFG3Channel 5 configuration register 3CH5_CFG3 Register (P0_R83)
0x54CH5_CFG4Channel 5 configuration register 4CH5_CFG4 Register (P0_R84)
0x55CH6_CFG0Channel 6 configuration register 0CH6_CFG0 Register (P0_R85)
0x57CH6_CFG2Channel 6 configuration register 2CH6_CFG2 Register (P0_R87)
0x58CH6_CFG3Channel 6 configuration register 3CH6_CFG3 Register (P0_R88)
0x59CH6_CFG4Channel 6 configuration register 4CH6_CFG4 Register (P0_R89)
0x5ACH7_CFG0Channel 7 configuration register 0CH7_CFG0 Register (P0_R90)
0x5CCH7_CFG2Channel 7 configuration register 2CH7_CFG2 Register (P0_R92)
0x5DCH7_CFG3Channel 7 configuration register 3CH7_CFG3 Register (P0_R93)
0x5ECH7_CFG4Channel 7 configuration register 4CH7_CFG4 Register (P0_R94)
0x5FCH8_CFG0Channel 8 configuration register 0CH8_CFG0 Register (P0_R95)
0x61CH8_CFG2Channel 8 configuration register 2CH8_CFG2 Register (P0_R97)
0x62CH8_CFG3Channel 8 configuration register 3CH8_CFG3 Register (P0_R98)
0x63CH8_CFG4Channel 8 configuration register 4CH8_CFG4 Register (P0_R99)
0x6BDSP_CFG0DSP configuration register 0DSP_CFG0 Register (P0_R107)
0x6CDSP_CFG1DSP configuration register 1DSP_CFG1 Register (P0_R108)
0x73IN_CH_ENInput channel enable configuration registerIN_CH_EN Register (P0_R115)
0x74ASI_OUT_CH_ENASI output channel enable configuration registerASI_OUT_CH_EN Register (P0_R116)
0x75PWR_CFGPower up configuration registerPWR_CFG Register (P0_R117)
0x76DEV_STS0Device status value register 0DEV_STS0 Register (P0_R118)
0x77DEV_STS1Device status value register 1DEV_STS1 Register (P0_R119)
0x7EI2C_CKSUM

I2C check sum register

I2C_CKSUM Register (P0_R126)