JAJSPG9H August   1987  – January 2023 SN65ALS180 , SN75ALS180

PRODUCTION DATA  

  1. 1 特長
  2. 2 概要
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics - Driver
    5. 5.5 Switching Characteristics - Driver
    6. 5.6 Symbol Equivalents
    7. 5.7 Electrical Characteristics - Receivers
    8. 5.8 Switching Characteristics - Receivers
    9. 5.9 Typical Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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発注情報

5.8 Switching Characteristics - Receivers

over recommended ranges of supply voltage and operating free-air temperature
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
tPLH Propagation delay time, low- to high-level output

VID = –1.5 V to 1.5 V,

See Figure 6-7

 CL = 15 pF, 9 14 19 ns
tPHL Propagation delay time, high- to low-level output

VID = –1.5 V to 1.5 V,

See Figure 6-7

 CL = 15 pF, 9 14 19 ns
Skew (|tPHL– tPLH|)

VID = –1.5 V to 1.5 V,

See Figure 6-7

 CL = 15 pF, 2 6 ns
tPZH Output enable time to high level CL = 15 pF, See Figure 6-8 7 14 ns
tPZL Output enable time to low level CL = 15 pF, See Figure 6-8 7 14 ns
tPHZ Output disable time from high level CL = 15 pF, See Figure 6-8 20 35 ns
tPLZ Output disable time from low level CL= 15 pF, See Figure 6-8 8 17 ns
(1) All typical values are at VCC = 5 V, TA = 25°C.