JAJSE45C February   2016  – December 2021 SN65DP141

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Switching Characteristics, I2C Interface
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DC and AC Independent Gain Control
      2. 8.3.2 Two-Wire Serial Interface and Control Logic
      3. 8.3.3 Bus Idle
      4. 8.3.4 Start Data Transfer
      5. 8.3.5 Stop Data Transfer
      6. 8.3.6 Data Transfer
      7. 8.3.7 Acknowledge
    4. 8.4 Device Functional Modes
      1. 8.4.1 TRACE and CABLE Equalization Modes
      2. 8.4.2 Control Modes
      3. 8.4.3 GPIO MODE
      4. 8.4.4 I2C Mode
    5. 8.5 Register Maps
      1. 8.5.1  Register 0x00 (General Device Settings) (offset = 00000000) [reset = 00000000]
      2. 8.5.2  Register 0x01 (Channel Enable) (offset = 00000000) [reset = 00000000]
      3. 8.5.3  Register 0x02 (Channel 0 Control Settings) (offset = 00000000) [reset = 00000000]
      4. 8.5.4  Register 0x03 (Channel 0 Enable Settings) (offset = 00000000) [reset = 00000000]
      5. 8.5.5  Register 0x05 (Channel 1 Control Settings) (offset = 00000000) [reset = 00000000]
      6. 8.5.6  Register 0x06 (Channel 1 Enable Settings) (offset = 00000000) [reset = 00000000]
      7. 8.5.7  Register 0x08 (Channel 2 Control Settings) (offset = 00000000) [reset = 00000000]
      8. 8.5.8  Register 0x09 (Channel 2 Enable Settings) (offset = 00000000) [reset = 00000000]
      9. 8.5.9  Register 0x0B (Channel 3 Control Settings) (offset = 00000000) [reset = 00000000]
      10. 8.5.10 Register 0x0C (Channel 3 Control Settings) (offset = 00000000) [reset = 00000000]
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Parameter Measurement Information

GUID-2D89A507-9370-4D5D-8690-E22BA9E378F8-low.gif Figure 7-1 Common Mode Output Voltage Test Circuit

GUID-A65E2668-2397-421C-953C-AB2685100476-low.gif Figure 7-2 Propagation Delay Input to Output

GUID-1EF77262-8A28-4146-B6C1-CAFCC4968D05-low.gif Figure 7-3 Output Rise and Fall Times

GUID-09BB1C3E-EC48-47D3-9631-7158BF26FDD7-low.gif Figure 7-4 Output Inter-Pair Skew

GUID-C288CBA7-5789-407A-9E6C-69A72E556A09-low.gif Figure 7-5 V(pre) and V(post) (test pattern is 1111111100000000 (8-1s, 8-0s))

GUID-7AEE5590-94BA-4960-8540-1536DD7A24F7-low.gif Figure 7-6 Receive Side Performance Test Circuit

GUID-5A1F5F78-826F-4090-A6FE-A44E3CEF1C98-low.gif Figure 7-7 Transmit Side Performance Test Circuit
GUID-9360C79D-AA89-4D1B-8DDB-B820BF13BA03-low.gif Figure 7-8 Equivalent Input Circuit

GUID-49C2FF21-F788-4893-9DCF-D3A69ED5DF0D-low.gif Figure 7-9 3-Level Input Biasing Network
GUID-554C6324-10B9-4765-A659-B7E24B89BC85-low.png Figure 7-10 Two – Wire Serial Interface Data Transfer
GUID-A687087B-088F-4410-916E-494B26C3FD59-low.png Figure 7-11 Two – Wire Serial Interface Timing Diagram